Opportunistic bus access latency

Abstract

A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.

1. A bus system, comprising:
 a plurality of signal driving devices coupled to a common signal bus, the plurality of signal driving devices comprising a first signal driving device and a second signal driving device; 
 a bus controller device coupled to the common signal bus, the bus controller device comprising delay compensation circuitry with a configurable delay for each of the plurality of signal driving devices, the delay compensation circuitry having a current delay chain configuration associated with a configurable delay for the first signal driving device; and 
 a compare circuit configured to compare the configurable delay associated with the first signal driving device to a configurable delay associated with the second signal driving device, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device to drive the common signal bus. 
 
     
     
       2. The bus system of  claim 1 , further comprising a configurable high offset register, wherein the compare circuit is further configured to adjust the configurable delay associated with the second signal driving device higher in response to contents of the high offset register. 
     
     
       3. The bus system of  claim 1 , further comprising a configurable low offset register, wherein the compare circuit is further configured to adjust the configurable delay associated with the second signal driving device lower in response to contents of the low offset register. 
     
     
       4. The bus system of  claim 1  wherein the bus controller device further comprises a controlling means responsive to the output of the compare circuit for reconfiguring the delay compensation circuitry in response to the output indicating that the current delay chain configuration cannot be used by the second signal driving device to drive the common signal bus. 
     
     
       5. The bus system of  claim 1 , wherein the bus controller device further comprises a user configurable register prescribing that the current delay chain configuration is always used by the second signal driving device to drive the common signal bus. 
     
     
       6. The bus system of  claim 1 , wherein the plurality of signal driving devices are memory devices and the common signal bus is a data bus. 
     
     
       7. The bus system of  claim 1 , wherein the plurality of signal driving devices are communication devices and the common signal bus is a communication system bus. 
     
     
       8. The bus system of  claim 1 , wherein the signal driving devices are coupled to the common signal bus via one or more of an electrical signal coupling, an electromagnetic signal coupling, and an optical signal coupling, and the bus controller device is coupled to the common signal bus via one or more of an electrical signal coupling, an electromagnetic signal coupling, and an optical signal coupling. 
     
     
       9. A method for driving a signal on a bus, the method comprising:
 receiving a first configurable delay amount associated with a first signal driving device; 
 receiving a second configurable delay amount associated with a current delay chain configuration; 
 determining if the first configurable delay amount is within a threshold of the second configurable delay amount; 
 driving a signal from the first signal driving device on the bus using the current delay chain configuration in response to determining that the first configurable delay amount is within the threshold of the second configurable delay amount; and 
 in response to determining that the first configurable delay amount is not within the threshold of the second configurable delay amount:
 modifying the current delay chain configuration to correspond to the first configurable delay amount; and 
 driving the signal from the first signal driving device on the bus using the modified delay chain configuration. 
 
 
     
     
       10. The method of  claim 9 , wherein the bus is a data bus in a memory system. 
     
     
       11. The method of  claim 9 , wherein the modifying includes modifying a subset of the current delay chain. 
     
     
       12. The method of  claim 9 , wherein the modifying includes modifying the entire current delay chain. 
     
     
       13. The method of  claim 9 , wherein the threshold is specified as a range that includes a high offset value and a low offset value. 
     
     
       14. The method of  claim 9 , further comprising:
 receiving an override instruction; and 
 in response to receiving the override instruction:
 bypassing the determining if the first configurable delay amount is within a threshold of the second configurable delay amount; and 
 driving the signal from the first signal driving device on the bus using the current delay chain configuration. 
 
 
     
     
       15. A computer program product for driving a signal on a bus, the computer program product comprising:
 a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for implementing a method, the method comprising: 
 receiving a first configurable delay amount associated with a first signal driving device; 
 receiving a second configurable delay amount associated with a current delay chain configuration; 
 determining if the first configurable delay amount is within a threshold of the second configurable delay amount; 
 driving a signal from the first signal driving device on the bus using the current delay chain configuration in response to determining that the first configurable delay amount is within the threshold of the second configurable delay amount; and 
 in response to determining that the first configurable delay amount is not within the threshold of the second configurable delay amount:
 modifying the current delay chain configuration to correspond to the first configurable delay amount; and 
 driving the signal from the first signal driving device on the bus using the modified delay chain configuration. 
 
 
     
     
       16. The computer program product of  claim 15 , wherein the bus is a data bus in a memory system. 
     
     
       17. The computer program product of  claim 15 , wherein the modifying includes modifying a subset of the current delay chain. 
     
     
       18. The computer program product of  claim 15 , wherein the modifying includes modifying the entire current delay chain. 
     
     
       19. The computer program product of  claim 15 , wherein the threshold is specified as a range that includes a high offset value and a low offset value. 
     
     
       20. The computer program product of  claim 15 , wherein the method further comprises:
 receiving an override instruction; and 
 in response to receiving the override instruction:
 bypassing the determining if the first configurable delay amount is within a threshold of the second configurable delay amount; and 
 driving the signal from the first signal driving device on the bus using the current delay chain configuration.