Inventor · disambiguated record
Michael A. Shinosky
Also filed as: SHINOSKY MICHAEL A · SHINOSKY MICHAEL ANTHONY
6 granted patents·1 pending application·13 citations·filing 2008–2015
76Inventor score
Top patents by PatentIndex Score
7 records- 0173US9851397B2Electromigration testing of interconnect analogues having bottom-connected sensory pinsGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 26, 2017·2 cites·18 claims
- 0271US7709401B2Method of making thermally programmable anti-reverse engineering interconnects wherein interconnects only conduct when heated above room temperatureIBM·Filed 2008·Granted May 4, 2010·4 cites·12 claims
- 0369US9453873B2Non-planar field effect transistor test structure and lateral dielectric breakdown testing methodIBM·Filed 2014·Granted Sep 27, 2016·2 cites·20 claims
- 0469US8754655B2Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migrationBROCHU JR DAVID G·Filed 2011·Granted Jun 17, 2014·3 cites·25 claims
- 0567US7843062B2Thermally programmable anti-reverse engineering interconnects wherein interconnects only conduct when heated above room temperatureIBM·Filed 2010·Granted Nov 30, 2010·2 cites·13 claims
- 0644US8525153B2Structure including voltage controlled negative resistanceCHEN FEN·Filed 2011·Granted Sep 3, 2013·0 cites·20 claims
- 0731US2016225919A1Device structure with negative resistance characteristicsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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