Inventor
DE LA MONEDA FRANCISCO H
US15 patents
Patents
15 patentsUS4102733AJul 25, 1978
Two and three mask process for IGFET fabrication
IBM60 citations96
US4072545AFeb 7, 1978
Raised source and drain igfet device fabrication
IBM64 citations95
US4139935AFeb 20, 1979
Over voltage protective device and circuits for insulated gate transistors
IBM40 citations92
US3958323AMay 25, 1976
Three mask self aligned IGFET fabrication process
IBM34 citations92
US4445267AMay 1, 1984
MOSFET Structure and process to form micrometer long source/drain spacing
IBM29 citations91
US4072868AFeb 7, 1978
FET inverter with isolated substrate load
IBM21 citations82
US4280855AJul 28, 1981
Method of making a dual DMOS device by ion implantation and diffusion
IBM27 citations81
US4016587AApr 5, 1977
Raised source and drain IGFET device and method
IBM26 citations81
US4102714AJul 25, 1978
Process for fabricating a low breakdown voltage device for polysilicon gate technology
IBM21 citations79
US4458406AJul 10, 1984
Making LSI devices with double level polysilicon structures
IBM7 citations73
US4149906AApr 17, 1979
Process for fabrication of merged transistor logic (MTL) cells
IBM10 citations73
US4138782AFeb 13, 1979
Inverter with improved load line characteristic
IBM19 citations73
US4115794ASep 19, 1978
Charge pumping device with integrated regulating capacitor and method for making same
IBM19 citations73
US4029522AJun 14, 1977
Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors
IBM18 citations73
US4078243AMar 7, 1978
Phototransistor array having uniform current response and method of manufacture
IBM14 citations69