Two and three mask process for IGFET fabrication

Abstract

Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level. The first mask of the two-mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions. After forming a thin oxide layer in these windows, the wafer is coated with successive layers of polysilicon and silicon nitride. Then, a second masking operation yields a pattern out of the polysilicon-nitride layer including gate electrodes and a top-lying interconnection level which abuts to openings etched through the thin oxide layer. Doping impurities are diffused therethrough to form source and drain regions and crossunders. After etching the nitride layer a silicide forming metal is deposited and sintered to form a silicide layer on all exposed silicon surfaces lowering the sheet resistance of the polysilicon layer and joining the interconnection pattern with the source and drain regions. The process is completed by removing the remaining unreacted metal using a maskless aqua regia etch.

We claim: 
     
       1. A process for fabricating an IGFET device, comprising: masking with a first mask and etching to define gate, source and drain openings in a thick insulating layer on a silicon semiconductor substrate;   coating all exposed surfaces with successive layers of thin insulating material and polysilicon;   masking with a second mask and etching said polysilicon and thin insulating layer in said source and drain regions and dip etching to remove said thin insulating material polysilicon composite layer therein;   introducing a conductivity enhancing dopant in the exposed source and drain regions;   coating all exposed surfaces with a silicide forming metal layer;   sintering said metal layer to form a silicide coating on said polysilicon layer in the gate region to form a gate electrode and on the exposed silicon in the source and drain regions to form source and drain contacts;   preferentially etching the unreacted portions of said metal layer;   whereby an IGFET device is fabricated.   
     
     
       2. The process of claim 1, wherein said silicide forming metal is selected from the group consisting of platinum, palladium and hafnium. 
     
     
       3. The process of claim 1, wherein said silicide forming metal is platinum. 
     
     
       4. The process of claim 1, wherein said second masking step includes the definition of polysilicon interconnection lines on said thick insulating layer, which are converted to a metal silicide during said sintering step. 
     
     
       5. The process of claim 4, wherein said polysilicon interconnection lines extend to the edge of said source and drain regions. 
     
     
       6. The process of claim 5, wherein said metal silicide formed in the portions of the silicon substrate exposed in said source and drain regions electrically contacts the metal silicide formed on said polysilicon lines. 
     
     
       7. The process of claim 1, which further comprises the step, following said step of preferentially etching the unreacted portions of said metal layer, of: depositing a second insulating layer over all exposed surfaces;   forming via holes in said second insulating layer over selected portions of said silicide coating;   depositing a second metal layer over said second insulating layer and said via holes;   etching said second metal layer to form a second level of interconnection lines which selectively and electrically connect with said silicide coating through said via holes.   
     
     
       8. The process of claim 1, wherein said thick and thin insulating layers are composed of a silicon oxide. 
     
     
       9. A two-mask process for fabricating an IGFET device, comprising: masking with a first mask and etching to define gate, source and drain openings in a thick oxide layer disposed on a silicon semiconductor substrate wafer;   coating a layer as thin oxide in said openings;   coating all surfaces with successive layers of polysilicon and silicon nitride;   masking with a second mask and etching said polysilicon and nitride layers to form gate electrodes and interconnection patterns disposed on said thin and thick oxide layers, leaving portions of said thin oxide uncovered to define source and drain contact windows;   exposing portions of said substrate by etching said uncovered thin oxide to form openings whose edges are self-aligned with respect to said interconnection line disposed on the remaining portion of thin oxide;   depositing doping impurities of polarity opposite to the substrate through said windows to form diffused regions for source and drain and crossunders composed of laterally merged diffused regions;   etching all of the remaining silicon nitride layer and coating all surfaces with a layer of silicide forming metal thicker than said remaining portions of thin oxide;   sintering said metal layer to form a silicide coating on said polysilicon gate electrode, interconnection pattern and on the portions of the source and drain regions exposed by said windows whereby the portion of the interconnection patterns disposed on the remaining thin oxide layer contacts said exposed portion of said substrate.   
     
     
       10. A three-mask process for fabricating an IGFET device, comprising the steps of: masking-etching to open windows in a silicon oxide layer initially formed on a semiconductor water, leaving exposed regions to be used as source, drain or a first-level interconnection;   diffusing through said windows doping impurities to form regions therein of polarity opposite to the substrate and enhance conductivity while simultaneously reforming the oxide layer in said windows;   masking-etching to open windows for the gate and contacts to the diffused regions and semiconductor substrate;   forming a thin oxide layer in said gate and contact windows;   depositing successive layers of polysilicon and silicon nitride on the wafer;   masking-etching to etch a pattern out of said double layer polysilicon and silicon nitride comprising gate electrodes and a second level interconnection grid which encompasses the contact holes opened through the thin oxide left exposed by the removed nitride-polysilicon, thereby aligning the polysilicon connection with the contact hole;   etching to remove the nitride layer;   coating the water with a silicide forming metal layer;   sintering the metal layer to form a silicide coating on all polysilicon surfaces and on exposed areas of the source and drain regions; and   preferentially etching the unreacted portions of the metal layer;   whereby arrays of IGFET devices can be formed and interconnected at a first level in the semiconductor wafer and a second level above the semiconductor surface.   
     
     
       11. The process of claim 10, wherein said silicide forming metal is selected from the group consisting of platinum, palladium and hafnium. 
     
     
       12. The process of claim 10, wherein said silicide forming metal is platinum. 
     
     
       13. The process of claim 10, which further comprises the step, following said step of preferentially etching the unreacted portions of said metal layer, of depositing a second insulating layer over all exposed surfaces;   forming via holes in said second insulating layer over selected portions of said silicide coating;   depositing a second metal layer over said second insulating layer and said via holes;   etching said second metal layer to form a second level of interconnection lines which selectively and electrically connect with said silicide coating through said via holes.