Inventor · disambiguated record
Francisco H. De La Moneda
Also filed as: DE LA MONEDA FRANCISCO · DE LA MONEDA FRANCISCO H
16 granted patents·427 citations·filing 1974–2003
95Inventor score
Top patents by PatentIndex Score
16 records- 0191US4072545ARaised source and drain igfet device fabricationIBM·Filed 1976·Granted Feb 7, 1978·64 cites·8 claims
- 0290US4102733ATwo and three mask process for IGFET fabricationIBM·Filed 1977·Granted Jul 25, 1978·60 cites·13 claims
- 0384US4016587ARaised source and drain IGFET device and methodIBM·Filed 1974·Granted Apr 5, 1977·26 cites·12 claims
- 0483US4139935AOver voltage protective device and circuits for insulated gate transistorsIBM·Filed 1977·Granted Feb 20, 1979·40 cites·9 claims
- 0578US4072868AFET inverter with isolated substrate loadIBM·Filed 1976·Granted Feb 7, 1978·21 cites·6 claims
- 0678US3958323AThree mask self aligned IGFET fabrication processIBM·Filed 1975·Granted May 25, 1976·34 cites·37 claims
- 0776US4445267AMOSFET Structure and process to form micrometer long source/drain spacingIBM·Filed 1981·Granted May 1, 1984·29 cites·24 claims
- 0873US4115794ACharge pumping device with integrated regulating capacitor and method for making sameIBM·Filed 1977·Granted Sep 19, 1978·19 cites·1 claims
- 0968US6953974B2EEPROM device and method for providing lower programming voltageTEXAS INSTRUMENTS INC·Filed 2003·Granted Oct 11, 2005·18 cites·33 claims
- 1064US4280855AMethod of making a dual DMOS device by ion implantation and diffusionIBM·Filed 1980·Granted Jul 28, 1981·27 cites·7 claims
- 1162US4138782AInverter with improved load line characteristicIBM·Filed 1977·Granted Feb 13, 1979·19 cites·4 claims
- 1261US4102714AProcess for fabricating a low breakdown voltage device for polysilicon gate technologyIBM·Filed 1976·Granted Jul 25, 1978·21 cites·5 claims
- 1360US4029522AMethod to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistorsIBM·Filed 1976·Granted Jun 14, 1977·18 cites·23 claims
- 1450US4078243APhototransistor array having uniform current response and method of manufactureIBM·Filed 1975·Granted Mar 7, 1978·14 cites·6 claims
- 1545US4149906AProcess for fabrication of merged transistor logic (MTL) cellsIBM·Filed 1977·Granted Apr 17, 1979·10 cites·2 claims
- 1637US4458406AMaking LSI devices with double level polysilicon structuresIBM·Filed 1981·Granted Jul 10, 1984·7 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →