Inventor · disambiguated record
Maureen A. Delaney
Also filed as: DELANEY MAUREEN · DELANEY MAUREEN A · DELANEY MAUREEN ANNE
26 granted patents·3 pending applications·122 citations·filing 1999–2018
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
29 records- 0196US9367322B1Age based fast instruction issueIBM·Filed 2015·Granted Jun 14, 2016·18 cites·20 claims
- 0289US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0386US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 0485US9389870B1Age based fast instruction issueIBM·Filed 2015·Granted Jul 12, 2016·3 cites·1 claims
- 0579US10133581B2Linkable issue queue parallel execution slice for a processorIBM·Filed 2015·Granted Nov 20, 2018·2 cites·20 claims
- 0679US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 0777US7243209B2Apparatus and method for speeding up access time of a large register file with wrap capabilityIBM·Filed 2005·Granted Jul 10, 2007·8 cites·20 claims
- 0875US8127116B2Dependency matrix with reduced area and power consumptionISLAM SAIFUL·Filed 2009·Granted Feb 28, 2012·10 cites·18 claims
- 0971US10949205B2Implementation of execution compression of instructions in slice target register file mapperIBM·Filed 2018·Granted Mar 16, 2021·1 cites·20 claims
- 1067US9983879B2Operation of a multi-slice processor implementing dynamic switching of instruction issuance orderIBM·Filed 2016·Granted May 29, 2018·1 cites·18 claims
- 1167US9971600B2Techniques to wake-up dependent instructions for back-to-back issue in a microprocessorIBM·Filed 2015·Granted May 15, 2018·1 cites·17 claims
- 1264US7663963B2Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file arrayIBM·Filed 2008·Granted Feb 16, 2010·2 cites·17 claims
- 1363US6463524B1Superscalar processor and method for incrementally issuing store instructionsIBM·Filed 1999·Granted Oct 8, 2002·44 cites·12 claims
- 1461US9965286B2Age based fast instruction issueIBM·Filed 2017·Granted May 8, 2018·0 cites·1 claims
- 1561US9870231B2Age based fast instruction issueIBM·Filed 2017·Granted Jan 16, 2018·0 cites·1 claims
- 1660US10140127B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 27, 2018·0 cites·13 claims
- 1760US10127047B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 13, 2018·0 cites·7 claims
- 1858US9880850B2Age based fast instruction issueIBM·Filed 2016·Granted Jan 30, 2018·0 cites·20 claims
- 1958US7400548B2Method for providing multiple reads/writes using a 2read/2write register file arrayIBM·Filed 2005·Granted Jul 15, 2008·1 cites·1 claims
- 2056US9952874B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 2155US9952861B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2015·Granted Apr 24, 2018·0 cites·13 claims
- 2252US2016202992A1Linkable issue queue parallel execution slice processing methodIBM·Filed 2015·Application pending·0 cites
- 2350US10078516B2Techniques to wake-up dependent instructions for back-to-back issue in a microprocessorIBM·Filed 2015·Granted Sep 18, 2018·0 cites·9 claims
- 2450US2016371090A1Techniques for improving issue of instructions with variable latencies in a microprocessorIBM·Filed 2016·Application pending·0 cites
- 2548US2016371091A1Techniques for improving issue of instructions with variable latencies in a microprocessorIBM·Filed 2015·Application pending·0 cites
- 2646US10031757B2Operation of a multi-slice processor implementing a mechanism to overcome a system hangIBM·Filed 2016·Granted Jul 24, 2018·0 cites·20 claims
- 2742US11150909B2Energy efficient source operand issueIBM·Filed 2015·Granted Oct 19, 2021·0 cites·20 claims
- 2842US7243170B2Method and circuit for reading and writing an instruction bufferIBM·Filed 2003·Granted Jul 10, 2007·0 cites·24 claims
- 2933US6535973B1Method and system for speculatively issuing instructionsIBM·Filed 1999·Granted Mar 18, 2003·5 cites·10 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →