Linkable issue queue parallel execution slice processing method

Abstract

A method of processing using an execution slice circuit including multiple parallel instruction execution slices provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The method also detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

What is claimed is: 
     
         1 . A method of executing program instructions by a processor core, the method comprising:
 receiving instructions of a first instruction stream at a master execution slice having a first issue queue;   receiving instructions of a second instruction stream and instructions of the first instruction stream that require a greater execution width greater than a lesser width of the master execution slice and the slave execution slice at a slave execution slice having a second issue queue;   detecting when a first instruction of the first instruction stream has the greater width; and   responsive to detecting that the first instruction has the greater width, controlling the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice with a control logic.   
     
     
         2 . The method of  claim 1 , further comprising:
 reserving the first issue cycle during an earlier issue cycle of the slave execution slice;   issuing an instruction of the second instruction stream from the slave execution slice while the control logic has reserved the first issue cycle; and   at a subsequent issue cycle, issuing the first instruction in parallel across the master execution slice and the slave execution slice.   
     
     
         3 . The method of  claim 2 , further comprising:
 responsive to detecting that the first instruction of the first instruction stream has the greater width, setting an allow bit corresponding to an issue queue entry of the first instruction that indicates that the first instruction is allowed for issue; and   issuing a corresponding portion of the first instruction in response to detecting that the allow bit is set at a next issue cycle.   
     
     
         4 . The method of  claim 3 , wherein the master execution slice comprises a first age array for storing first indications of a first sequence in which instructions of the first instruction stream that have been dispatched to the master execution slice but not yet issued, wherein the method further comprises:
 retrieving an entry from the first age array corresponding to an oldest instruction present in the first age array that is ready for issue; and   comparing the retrieved entry to a mask indicating which entries have the greater width, wherein the first instruction of the first instruction stream is the oldest instruction present in the first age array, whereby the control logic detects that the first instruction of the first instruction stream has the greater width.   
     
     
         5 . The method of  claim 4 , wherein the slave execution slice comprises a second age array for storing second indications of a second sequence in which instructions of the second instruction stream that have been dispatched to the slave execution slice but not yet issued, wherein the method further comprises:
 at issue cycles, retrieving an oldest allowed entry of the first age array and an oldest allowed entry of the second age array; and   using the retrieved entries to issue corresponding instructions for execution by the master execution slice the slave execution slice.   
     
     
         6 . The method of  claim 5 , further comprising responsive to detecting that the first instruction of the first instruction stream has the greater width, overwriting a bit field indicating allowed entries in the second age array to a value specifying a portion of the first instruction corresponding to the slave execution slice to be issued by the slave execution slice at a next execution cycle.