Inventor

OOI KOOI CHI

MY60 patents

⚠️ This page may combine multiple inventors who share the name “OOI KOOI CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OOI KOOI CHI

INTEL CORP

Stacked die semiconductor package

Stacked die package

Stacked-die packages with silicon vias and surface activated bonding

Systems in packages including wide-band phased-array antennas and methods of assembling same

Systems in packages including wide-band phased-array antennas and methods of assembling same

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Package on package design to improve functionality and efficiency

Wearable electronic devices and components thereof

Wearable electronic devices and components thereof

Ring-in-ring configurable-capacitance stiffeners and methods of assembling same

Methods and apparatus to improve data training of a machine learning model using a field programmable gate array

Hybrid ball grid array package for high speed interconnects

Integrated bridge for die-to-die interconnects

Substrate with gradiated dielectric for reducing impedance mismatch

Electronic packages with stacked sitffeners and methods of assembling same

Flexible system-in-package solutions for wearable devices

Foldable fabric-based packaging solution

Methods and apparatus for allocating a workload to an accelerator using machine learning

Ring-in-ring configurable-capacitance stiffeners and methods of assembling same

Evaluating risk factors of proposed vehicle maneuvers using external and internal data

Flexible packaging architecture

Bandwidth allocation for network packet traffic

Semiconductor packages for stacked memory-on-package (SMOP) and methods of manufacturing the same

Semiconductor package with hybrid mold layers

Integrated bridge for die-to-die interconnects

Substrate with gradiated dielectric for reducing impedance mismatch

Embedded reference layers for semiconductor package substrates

Interposer for hybrid interconnect geometry

Overhang bridge interconnect

Interconnect core

Vertical power plane module for semiconductor packages

Embedded reference layers for semiconductor package substrates

Multi-conductor interconnect structure for a microelectronic device

Stacked dice systems

Stacked package assembly with voltage reference plane

Encapsulated vertical interconnects for high-speed applications and methods of assembling same

Methods and apparatus for allocating a workload to an accelerator using machine learning

Encapsulated vertical interconnects for high-speed applications and methods of assembling same

Vertical die-to-die interconnects bridge

Computer-assisted or autonomous driving vehicle incident management method and apparatus

Semiconductor device and system

Integrated bridge frame for package substrate

CHEAH BOK ENG

High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same

Method to enable controlled side chip interconnection for 3D integrated packaging system

Stacked die package

High density second level interconnection for bumpless build up layer (BBUL) packaging technology

PERIAMAN SHANGGAR

Die backside wire bond technology for single or stacked die package

Die backside metallization and surface activated bonding for stacked die packages

CHEW YEN HSIANG

Firmware verification using system memory error check logic