Vertical power plane module for semiconductor packages

Abstract

The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a package substrate; 
 a base die on and electrically coupled to the package substrate; 
 at least one power plane module on the package substrate at a periphery of the base die, the power plane module comprising:
 a top surface and a bottom surface; and 
 at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate; and 
 
 a semiconductor device comprising a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device is electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the at least one vertical interleaving metal layer further comprises a plurality of interleaving metal layers, each of the plurality of interleaving metal layers further comprises:
 a top portion coupled to the semiconductor device; and 
 a bottom portion coupled to the package substrate, wherein the bottom portion has a larger width than a width of the top portion. 
 
     
     
       3. The semiconductor package of  claim 2 , wherein the width of the bottom portion is at least one and a half times larger than the width of the top portion. 
     
     
       4. The semiconductor package of  claim 2 , wherein the plurality of interleaving metal layers further comprises at least one ground reference voltage plane and at least one power reference voltage plane. 
     
     
       5. The semiconductor package of  claim 2 , wherein the power plane module further comprises at least one passive component. 
     
     
       6. The semiconductor package of  claim 5 , wherein the passive component is electrically coupled to at least one metal layer of the plurality of interleaving metal layers. 
     
     
       7. The semiconductor package of  claim 5 , wherein the passive component comprises a multi-layer ceramic capacitor and/or a silicon capacitor. 
     
     
       8. The semiconductor package of  claim 2 , wherein the power plane module further comprises a plurality of trenches on one or more of the plurality of interleaving metal layers. 
     
     
       9. The semiconductor package of  claim 8 , wherein the plurality of trenches are isolated by dielectric layers. 
     
     
       10. The semiconductor package of  claim 8 , wherein the plurality of trenches are arranged in an interdigital arrangement. 
     
     
       11. The semiconductor package of  claim 1 , wherein the plurality of interleaving metal layers are isolated by dielectric layers. 
     
     
       12. The semiconductor package of  claim 4 , wherein the ground reference voltage plane and the power reference voltage plane are parallel to each other. 
     
     
       13. The semiconductor package of  claim 1 , wherein the power plane module further comprises a first section at the periphery of the base die with a first bottom portion disposed on the package substrate, and a second section at a periphery of the package substrate with a second bottom portion disposed on a motherboard. 
     
     
       14. A computing device comprising:
 a circuit board; and 
 a semiconductor package coupled to the circuit board, wherein the semiconductor package comprises:
 a package substrate; 
 
 a base die on and electrically coupled to the package substrate; 
 at least one power plane module on the package substrate at a periphery of the base die, the power plane module comprising:
 a top surface and a bottom surface; and 
 at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate; and 
 
 a semiconductor device comprising a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device is electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module. 
 
     
     
       15. The computing device of  claim 14 ,
 wherein the at least one vertical interleaving metal layer further comprises a plurality of interleaving metal layers, each of the plurality of interleaving metal layers further comprises:
 a top portion coupled to the semiconductor device; and 
 a bottom portion coupled to the package substrate, wherein the bottom portion has a larger width than a width of the top portion. 
 
 
     
     
       16. A method comprising:
 forming a package substrate; 
 forming a base die on the package substrate; 
 forming a power plane module at a periphery of the base die, the power plane module comprising:
 a top surface and a bottom surface; and 
 at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate; 
 
 forming a semiconductor device comprising a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device is electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module. 
 
     
     
       17. The method of  claim 16 ,
 wherein the at least one vertical interleaving metal layer further comprises a plurality of interleaving metal layers, each of the plurality of interleaving metal layers further comprises:
 a top portion coupled to the semiconductor device; and 
 a bottom portion coupled to the package substrate, wherein the bottom portion has a larger width than a width of the top portion. 
 
 
     
     
       18. The method of  claim 17 , further comprising coupling at least one passive component to the plurality of interleaving metal layers. 
     
     
       19. The method of  claim 17 , further comprising coupling a plurality of trenches to one or more of the plurality of interleaving metal layers. 
     
     
       20. The method of  claim 19 , further comprising arranging the trenches in an interdigital arrangement.