Inventor

FULFORD JR H JIM

US186 patents

⚠️ This page may combine multiple inventors who share the name “FULFORD JR H JIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FULFORD JR H JIM

ADVANCED MICRO DEVICES INC

Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit

Method and apparatus for in situ anneal during ion implant

Oxide liner for high reliability with reduced encroachment of the source/drain region

Dissolvable dielectric method

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

Method of making IGFETs in densely and sparsely populated areas of a substrate

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate

Method of making NMOS and PMOS devices with reduced masking steps

Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen

Transistor with buried insulative layer beneath the channel region

Method of channel doping using diffusion from implanted polysilicon

Trench transistor with localized source/drain regions implanted through selectively grown oxide layer

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Interlevel dielectric with air gaps to reduce permitivity

Multiple split gate semiconductor device and fabrication method

Integrated circuit gate conductor which uses layered spacers to produce a graded junction

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

Interlevel dielectric with air gaps to lessen capacitive coupling

Trench transistor with insulative spacers

Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions

High-reliability damascene interconnect formation for semiconductor fabrication

Ultrathin silicon nitride containing sidewall spacers for improved transistor performance

Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias

Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process

Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate

Method of processing a semiconductor wafer for controlling drive current

Method of making an IGFET with a multilevel gate

Method for achieving global planarization by forming minimum mesas in large field areas

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Reticle that compensates for radiation-induced lens error in a photolithographic system

Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles

Subtrench conductor formation with large tilt angle implant

Integrated circuit gate conductor which uses layered spacers to produce a graded junction

Individually controllable radiation sources for providing an image pattern in a photolithographic system

Interlevel dielectric with air gaps to lessen capacitive coupling

Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Multiple spacer formation/removal technique for forming a graded junction

Method of forming a shallow junction by diffusion from a silicon-based spacer

Semiconductor wafer with enhanced pre-process denudation and process-induced gettering

Ultra thin high K spacer material for use in transistor fabrication

Method of making non-volatile memory device having a floating gate with enhanced charge retention

Method for achieving a highly reliable oxide film

ADVANCED MICRO DEVCIES INC

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect