Integrated circuit gate conductor which uses layered spacers to produce a graded junction

Abstract

A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed. Each time, the implants are performed with a lower energy and with a lower dosage so as to grade the junction with lighter concentrations and energies as the implant areas approach the channel. Reversing the implantation process enables high-temperature thermal anneals required for high-concentration low-diffusivity dopants to be performed first. The LDD implant comprises dopants of lower concentration and higher diffusivity requiring lower temperature anneals. Performing lower temperature anneals later in the sequence affords a lessened opportunity for undesirable short-channel effects.

What is claimed is: 
     
       1. An integrated circuit, comprising: a gate conductor residing upon a semiconductor topography, said gate conductor is confined between a pair of opposing sidewall surfaces;   a first implant area aligned to said opposing sidewall surfaces and extending to a first depth below a surface of said semiconductor topography, wherein said first implant area comprises a first dopant concentration;   a second implant area spaced from said opposing sidewall surfaces by a first distance, wherein said second implant area extends to a second depth below said surface which is greater than said first depth, and wherein said second implant area comprises a second dopant concentration which is greater than said first dopant concentration;   a third implant area spaced from said opposing sidewall surfaces by a second distance which is greater than said first distance, wherein said third implant area extends below said surface to a third depth which is greater than said second depth, and wherein said third implant area comprises a third dopant concentration which is greater than said second dopant concentration; and   at least two layers having dissimilar etch characteristics configured upon said opposing sidewall surfaces of said gate conductor.   
     
     
       2. The integrated circuit as recited in claim 1, wherein said layers comprise an oxide layer interposed between a pair of nitride layers. 
     
     
       3. The integrated circuit as recited in claim 1, wherein said layers comprise an oxide layer interposed between a pair of polycrystalline layers. 
     
     
       4. The integrated circuit as recited in claim 1, wherein said layers comprise a nitride layer interposed between a thermally grown oxide and a chemical vapor deposited oxide. 
     
     
       5. The integrated circuit as recited in claim 1, wherein said layers comprise a polycrystalline layer interposed between a thermally grown oxide and a chemical vapor deposited oxide. 
     
     
       6. The integrated circuit as recited in claim 1, wherein each of said layers is formed in sequence. 
     
     
       7. The integrated circuit as recited in claim 1, wherein one of said layers comprises a first exterior sidewall spaced from said opposing sidewall surfaces of said gate conductor by said first distance, and wherein another of said layers comprises a second exterior sidewall spaced from said opposing sidewall surfaces by said second distance. 
     
     
       8. The integrated circuit as recited in claim 7, wherein said second implant region comprises a second interior lateral surface aligned to said first exterior sidewall, and wherein said third implant region comprises a third interior lateral surface aligned to said second exterior sidewall.