Inventor · disambiguated record
Mark I. Gardner
Also filed as: GARDNER MARK · GARDNER MARK I
619 granted patents·75 pending applications·16,803 citations·filing 1992–2025
99Inventor score
Files withADVANCED MICRO DEVICES INC504TOKYO ELECTRON LTD171ADVANCED MICRODEVICES INC2ADVANCED MICRON DEVICES INC2INFINEON TECHNOLOGIES AG2
Top patents by PatentIndex Score
694 records- 0199US11527545B2Architecture design and process for 3D logic and 3D memoryTOKYO ELECTRON LTD·Filed 2020·Granted Dec 13, 2022·10 cites·20 claims
- 0299US6111260AMethod and apparatus for in situ anneal during ion implantADVANCED MICRO DEVICES INC·Filed 1997·Granted Aug 29, 2000·305 cites·19 claims
- 0398US11302587B2Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devicesTOKYO ELECTRON LTD·Filed 2020·Granted Apr 12, 2022·5 cites·20 claims
- 0498US6225168B1Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereofADVANCED MICRO DEVICES INC·Filed 1998·Granted May 1, 2001·239 cites·20 claims
- 0598US6080640AMetal attachment method and structure for attaching substrates at low temperaturesADVANCED MICRO DEVICES INC·Filed 1998·Granted Jun 27, 2000·291 cites·17 claims
- 0698US6075268AUltra high density inverter using a stacked transistor arrangementADVANCED MICRO DEVICES INC·Filed 1998·Granted Jun 13, 2000·256 cites·11 claims
- 0798US5905285AUltra short trench transistors and process for making sameADVANCED MICRO DEVICES INC·Filed 1998·Granted May 18, 1999·188 cites·8 claims
- 0897US11631671B23D complementary metal oxide semiconductor (CMOS) device and method of forming the sameTOKYO ELECTRON LTD·Filed 2020·Granted Apr 18, 2023·5 cites·23 claims
- 0997US6255698B1Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuitADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 3, 2001·202 cites·18 claims
- 1097US6093611AOxide liner for high reliability with reduced encroachment of the source/drain regionADVANCED MICRO DEVICES INC·Filed 1997·Granted Jul 25, 2000·294 cites·25 claims
- 1197US5770483AMulti-level transistor fabrication method with high performance drain-to-gate connectionADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 23, 1998·256 cites·18 claims
- 1296US6150286AMethod of making an ultra thin silicon nitride filmADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 21, 2000·167 cites·18 claims
- 1396US6015739AMethod of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constantADVANCED MICRO DEVICES INC·Filed 1997·Granted Jan 18, 2000·166 cites·17 claims
- 1495US6210999B1Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devicesADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 3, 2001·211 cites·28 claims
- 1595US5793090AIntegrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performanceADVANCED MICRO DEVICES INC·Filed 1997·Granted Aug 11, 1998·123 cites·18 claims
- 1694US11195832B2High performance nanosheet fabrication method with enhanced high mobility channel elementsTOKYO ELECTRON LTD·Filed 2019·Granted Dec 7, 2021·8 cites·8 claims
- 1793US11652139B2Three-dimensional universal CMOS deviceTOKYO ELECTRON LTD·Filed 2021·Granted May 16, 2023·2 cites·19 claims
- 1893US6200865B1Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gateADVANCED MICRO DEVICES INC·Filed 1998·Granted Mar 13, 2001·116 cites·20 claims
- 1993US6060345AMethod of making NMOS and PMOS devices with reduced masking stepsADVANCED MICRO DEVICES INC·Filed 1997·Granted May 9, 2000·114 cites·22 claims
- 2093US5888880ATrench transistor with localized source/drain regions implanted through selectively grown oxide layerADVANCED MICRO DEVICES INC·Filed 1996·Granted Mar 30, 1999·113 cites·43 claims
- 2192US11133310B2Method of making multiple nano layer transistors to enhance a multiple stack CFET performanceTOKYO ELECTRON LTD·Filed 2019·Granted Sep 28, 2021·6 cites·8 claims
- 2292US6150222AMethod of making a high performance transistor with elevated spacer formation and self-aligned channel regionsADVANCED MICRO DEVICES INC·Filed 1999·Granted Nov 21, 2000·106 cites·39 claims
- 2392US6097096AMetal attachment method and structure for attaching substrates at low temperaturesADVANCED MICRO DEVICES INC·Filed 1997·Granted Aug 1, 2000·116 cites·9 claims
- 2492US5907780AIncorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantationADVANCED MICRO DEVICES INC·Filed 1998·Granted May 25, 1999·96 cites·15 claims
- 2592US5885877AComposite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectricADVANCED MICRO DEVICES INC·Filed 1997·Granted Mar 23, 1999·107 cites·27 claims
- 2692US5837572ACMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted thereinADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 17, 1998·103 cites·21 claims
- 2791US11557657B2High density 3D layout enhancement of multiple CMOS devicesTOKYO ELECTRON LTD·Filed 2021·Granted Jan 17, 2023·2 cites·9 claims
- 2891US11557655B2Device and method of forming with three-dimensional memory and three-dimensional logicTOKYO ELECTRON LTD·Filed 2020·Granted Jan 17, 2023·2 cites·12 claims
- 2991US11362091B2Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performanceTOKYO ELECTRON LTD·Filed 2019·Granted Jun 14, 2022·5 cites·11 claims
- 3091US6373113B1Nitrogenated gate structure for improved transistor performance and method for making sameADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 16, 2002·81 cites·9 claims
- 3191US6355955B1Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formationADVANCED MICRO DEVICES INC·Filed 2000·Granted Mar 12, 2002·64 cites·8 claims
- 3291US6169306B1Semiconductor devices comprised of one or more epitaxial layersADVANCED MICRO DEVICES INC·Filed 1998·Granted Jan 2, 2001·92 cites·44 claims
- 3391US6140688ASemiconductor device with self-aligned metal-containing gateADVANCED MICRO DEVICES INC·Filed 1998·Granted Oct 31, 2000·88 cites·20 claims
- 3491US6074919AMethod of forming an ultrathin gate dielectricADVANCED MICRO DEVICES INC·Filed 1999·Granted Jun 13, 2000·99 cites·20 claims
- 3590US11410888B2Method of making 3D CMOS with integrated channel and S/D regionsTOKYO ELECTRON LTD·Filed 2020·Granted Aug 9, 2022·2 cites·20 claims
- 3690US11282828B2High density architecture design for 3D logic and 3D memory circuitsTOKYO ELECTRON LTD·Filed 2020·Granted Mar 22, 2022·2 cites·20 claims
- 3790US6245652B1Method of forming ultra thin gate dielectric for high performance semiconductor devicesADVANCED MICRO DEVICES INC·Filed 2000·Granted Jun 12, 2001·57 cites·32 claims
- 3890US6103559AMethod of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabricationAMD INC ADVANCED MICRO DEVICES·Filed 1999·Granted Aug 15, 2000·108 cites·20 claims
- 3990US6084280ATransistor having a metal silicide self-aligned to the gateADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 4, 2000·82 cites·41 claims
- 4090US6048766AFlash memory device having high permittivity stacked dielectric and fabrication thereofADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 11, 2000·91 cites·19 claims
- 4190US5918129AMethod of channel doping using diffusion from implanted polysiliconADVANCED MICRO DEVICES INC·Filed 1997·Granted Jun 29, 1999·110 cites·18 claims
- 4290US5882993AIntegrated circuit with differing gate oxide thickness and process for making sameADVANCED MICRO DEVICES INC·Filed 1996·Granted Mar 16, 1999·73 cites·19 claims
- 4390US5869379AMethod of forming air gap spacer for high performance MOSFETS'ADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 9, 1999·73 cites·12 claims
- 4490US5847428AIntegrated circuit gate conductor which uses layered spacers to produce a graded junctionADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 8, 1998·76 cites·8 claims
- 4590US5811347ANitrogenated trench liner for improved shallow trench isolationADVANCED MICRO DEVICES INC·Filed 1996·Granted Sep 22, 1998·105 cites·13 claims
- 4689US11264289B2Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacksTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·2 cites·19 claims
- 4789US11251159B2High performance CMOS using 3D device layoutTOKYO ELECTRON LTD·Filed 2020·Granted Feb 15, 2022·2 cites·12 claims
- 4889US11171208B2High performance circuit applications using stacked 3D metal linesTOKYO ELECTRON LTD·Filed 2020·Granted Nov 9, 2021·2 cites·18 claims
- 4989US6191446B1Formation and control of a vertically oriented transistor channel lengthADVANCED MICRO DEVICES INC·Filed 1998·Granted Feb 20, 2001·80 cites·15 claims
- 5089US6162688AMethod of fabricating a transistor with a dielectric underlayer and device incorporating sameADVANCED MICRO DEVICES INC·Filed 1999·Granted Dec 19, 2000·80 cites·20 claims
Showing the top 50 of 694 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Mark I. Gardner files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →