Inventor

JONES JR OSCAR FREDERICK

US27 patents

⚠️ This page may combine multiple inventors who share the name “JONES JR OSCAR FREDERICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JONES JR OSCAR FREDERICK

UNITED MEMORIES INC

Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture

Data inversion register technique for integrated circuit memory testing

Clock controlled power-down state

Refresh initiated precharge technique for dynamic random access memory arrays using look-ahead refresh

Simultaneous function dynamic random access memory device technique

Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry

Automatic delay technique for early read and write operations in synchronous dynamic random access memories

Look-ahead refresh for an integrated circuit memory

Low skew signal generation circuit

Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

Low skew clock distribution tree

Dual-complementary integrating duty cycle detector with dead band noise rejection

SONY CORP

Non-contiguous masked refresh for an integrated circuit memory

Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM

Dual word line mode for DRAMs

Dual access DRAM

PARRIS MICHAEL C

Data inversion register technique for integrated circuit memory testing

Error correction code (ECC) circuit test mode

JONES JR OSCAR FREDERICK

Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

RAMTRON INT CORP

Enhanced DRAM with single row SRAM cache for all device read operations

IBM

Cached synchronous DRAM architecture having a mode register programmable cache policy

PURPLE MOUNTAIN SERVER LLC

Enhanced DRAM with embedded registers

PROMOS TECHNOLOGIES INC

Time data compression technique for high speed integrated circuit memory devices

MOSEL VITELIC INC

System and method for high speed integrated circuit device testing utilizing a lower speed test environment

PROMOS TECHNOLOGIES PTE LTD

Low skew differential amplifier using tail voltage reference and tail feedback