Data inversion register technique for integrated circuit memory testing

Abstract

A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

What is claimed is: 
     
       1. A testing technique for an integrated circuit device including a memory array, said technique comprising:
 determining a first pattern of data inputs to be applied to said memory array; 
 inverting selected one or ones of data inputs of said first pattern of data inputs to create a second pattern of data inputs; 
 applying said second pattern of data inputs including said inverted selected ones to said memory array; 
 reading out a contents of said memory array; 
 further inverting said previously inverted selected ones of said applied pattern from said read out contents 
 inverting one or ones of said read out contents which correspond, respectively, to said inverted selected one or ones of data inputs of said first pattern of data inputs to create a read out pattern; and 
 comparing said applied first pattern of data inputs with said read out contents pattern. 
 
     
     
       2. The technique of  claim 1  wherein said determining of said first pattern of data inputs comprises:
 selecting is a pattern of said data input inputs intended to test an input/output portion of said integrated circuit device. 
 
     
     
       3. The technique of  claim 2  wherein said selecting of said first pattern comprises:
 utilizing of data inputs includes data stripes in said selected pattern. 
 
     
     
       4. The technique of  claim 1  wherein said determining of said first pattern of data inputs comprises:
 selecting is a pattern of said data input inputs intended to test said memory array of said integrated circuit device. 
 
     
     
       5. The technique of claim  2  4 wherein said selecting of said first pattern comprises:
 utilizing of data inputs includes column stripes in said selected pattern. 
 
     
     
       6. The technique of  claim 1  wherein a number of said data inputs of said first pattern is less than the a width of a data bus of said memory array data bus. 
     
     
       7. The technique of  claim 6  wherein said number of said data inputs is one. 
     
     
       8. A testing technique for an integrated circuit device including a memory array, said technique comprising:
 dynamically providing a first pattern of data inputs to be applied to said memory array; 
 inverting selected one or ones of data inputs of said first pattern of data inputs to create a second pattern of data inputs; 
 applying said second pattern of data inputs including said inverted selected ones to said memory array; 
 reading out a contents of said memory array; 
 further inverting said previously inverted selected ones of said applied pattern from said read out contents 
 inverting one or ones of said read out contents which correspond, respectively, to said inverted selected one or ones of data inputs of said first pattern of data inputs to create a read out pattern; and 
 comparing said applied pattern of data inputs with said read out contents pattern. 
 
     
     
       9. The technique of  claim 8  wherein said dynamically providing said first pattern of data inputs comprises:
 selecting is a pattern of said data input inputs intended to test an input/output portion of said integrated circuit device. 
 
     
     
       10. The technique of  claim 9  wherein said selecting of said first pattern comprises:
 utilizing of data inputs includes data stripes in said selected pattern. 
 
     
     
       11. The technique of  claim 8  wherein said dynamically providing said first pattern of data inputs comprises:
 selecting is a pattern of said data input inputs intended to test said memory array of said integrated circuit device. 
 
     
     
       12. The technique of claim  9  11 wherein said selecting of said first pattern comprises:
 utilizing of data inputs includes column stripes in said selected pattern. 
 
     
     
       13. The technique of  claim 8  wherein said dynamically providing said first pattern of data inputs is carried out by means of a programmable register. 
     
     
       14. The technique of  claim 8  wherein a number of said data inputs of said first pattern is less than the a width of a data bus of said memory array data bus. 
     
     
       15. The technique of  claim 14  wherein said number of said data inputs is one. 
     
     
       16. An apparatus comprising a circuit configured for testing of an integrated circuit device including a memory array,
 wherein the circuit is configured for:
 determining a first pattern of data inputs; 
 inverting selected one or ones of data inputs of said first pattern of data inputs to create a second pattern of data inputs; 
 applying said second pattern of data inputs to said memory array; 
 reading out contents of said memory array; 
 inverting one or ones of said read out contents which correspond, respectively, to said inverted selected one or ones of data inputs of said first pattern of data inputs to create a read out pattern; and 
 comparing said first pattern of data inputs with said read out pattern. 
   
     
     
       17. The apparatus of claim 16, wherein said first pattern of data inputs is a pattern of data inputs intended to test an input/output portion of said integrated circuit device. 
     
     
       18. The apparatus of claim 17, wherein said first pattern of data inputs includes data stripes. 
     
     
       19. The apparatus of claim 16, wherein said first pattern of data inputs is a pattern of data inputs intended to test said memory array of said integrated circuit device. 
     
     
       20. The apparatus of claim 19, wherein said first pattern of data inputs includes column stripes. 
     
     
       21. The apparatus of claim 16, wherein a number of said data inputs of said first pattern is less than a width of a data bus of said memory array. 
     
     
       22. An apparatus comprising a circuit configured for testing of an integrated circuit device including a memory array,
 wherein the circuit is configured for:
 dynamically providing a first pattern of data inputs; 
 inverting selected one or ones of data inputs of said first pattern of data inputs to create a second pattern of data inputs; 
 applying said second pattern of data inputs to said memory array; 
 reading out contents of said memory array; 
 inverting one or ones of said read out contents which correspond, respectively, to said inverted selected one or ones of data inputs of said first pattern of data inputs to create a read out pattern; and 
 comparing said first pattern of data inputs with said read out pattern. 
   
     
     
       23. The apparatus of claim 22, wherein said first pattern of data inputs is a pattern of data inputs intended to test an input/output portion of said integrated circuit device. 
     
     
       24. The apparatus of claim 23, wherein said first pattern includes data stripes. 
     
     
       25. The apparatus of claim 22, wherein said first pattern of data inputs is a pattern of data inputs intended to test said memory array of said integrated circuit device. 
     
     
       26. The apparatus of claim 25, wherein said first pattern of data inputs includes column stripes. 
     
     
       27. The apparatus of claim 22, wherein said dynamically providing said first pattern of data inputs is carried out by means of a programmable register. 
     
     
       28. The apparatus of claim 22, wherein a number of said data inputs of said first pattern is less than a width of a data bus of said memory array.