Inventor

PARRIS MICHAEL C

US48 patents

⚠️ This page may combine multiple inventors who share the name “PARRIS MICHAEL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARRIS MICHAEL C

UNITED MEMORIES INC

Shift redundancy scheme for wordlines in memory circuits

Data inversion register technique for integrated circuit memory testing

Simultaneous function dynamic random access memory device technique

Precharge and reference voltage technique for dynamic random access memories

Technique for efficient logic power gating with data retention in integrated circuit devices

Circuit and method for accessing memory cells of a memory device

DRAM having self-timed burst refresh mode

DRAM variable row select

Short-circuit charge-sharing technique for integrated circuit devices

Data bus charge-sharing technique for integrated circuit devices

Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays

Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time

Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices

Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry

Automatic delay technique for early read and write operations in synchronous dynamic random access memories

Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values

Bitline reference voltage circuit

Asynchronous input data path technique for increasing speed and reducing latency in integrated circuit devices incorporating dynamic random access memory (DRAM) arrays and embedded DRAM

High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages

Data path decoding technique for an embedded memory array

Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

Optimized charge sharing for data bus skew applications

Low skew clock distribution tree

Multiple bus charge sharing

Data path decoding technique for an embedded memory array

SONY CORP

Powergating method and apparatus

Powergate control using boosted and negative voltages

Non-contiguous masked refresh for an integrated circuit memory

Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM

Dual word line mode for DRAMs

Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays

Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM

Dual access DRAM

PARRIS MICHAEL C

Data inversion register technique for integrated circuit memory testing

DRAM security erase

Error correction code (ECC) circuit test mode

Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM

TESSERA INC

DRAM security erase

DRAM security erase

DRAM security erase

Power boosting circuit for semiconductor packaging

MOSEL VITELIC INC

Dynamic predecoder circuitry for memory circuits

Self-timed data amplifier and method for an integrated circuit memory device

System and method for high speed integrated circuit device testing utilizing a lower speed test environment

CRISP RICHARD DEWITT

Power boosting circuit for semiconductor packaging

PROMOS TECHNOLOGIES INC

Time data compression technique for high speed integrated circuit memory devices

UNITED MEMEORIES INC

Delayed start oscillator circuit

PROMOS TECHNOLOGIES PTE LTD

Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM