Data path decoding technique for an embedded memory array

Abstract

A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

What is claimed is:  
     
       1. An integrated circuit device including a memory array having a data path comprising: 
       N read column lines;  
       N write column lines  
       first and second groups of N sense amplifiers respectively couplable to first and second pairs of complementary local data read lines in response to signals on said N read column lines and to first and second pairs of complementary local data write lines in response to signals on said N write column lines;  
       first and second local read circuits respectively coupled to said first and second pairs of complementary local data read lines;  
       first and second local write circuits respectively coupled to said first and second pairs of complementary local data write lines;  
       complementary global data read lines selectively couplable to either of said first and second pairs of complementary local data read lines in response to first and second read enable signals applied to said first and second local read circuits; and  
       complementary global data write lines selectively couplable to either of said first and second pairs of complementary local data write lines in response to first and second write enable signals applied to said first and second local write circuits.  
     
     
       2. The integrated circuit device of  claim 1  wherein N=8. 
     
     
       3. The integrated circuit device of  claim 1  wherein said N read column lines and said N write column lines comprise pre-decoded column lines. 
     
     
       4. The integrated circuit device of  claim 1  further comprising: 
       first and second switching devices for selectively coupling designated ones of said sense amplifiers to said first and second pairs of complementary local data read lines in response to said signals on said N read column lines.  
     
     
       5. The integrated circuit device of  claim 4  further comprising: 
       third and fourth switching devices for selectively coupling designated ones of said sense amplifiers to said first and second pairs of complementary local data write lines in response to said signals on said N write column lines.  
     
     
       6. The integrated circuit device of  claim 5  wherein said first, second, third-and fourth switching devices comprise MOS transistors. 
     
     
       7. The integrated circuit device of  claim 6  wherein said MOS transistors comprise N-channel devices. 
     
     
       8. The integrated circuit device of  claim 2  wherein said first and second read enable and first and second write enable signals are respectively complementary. 
     
     
       9. The integrated circuit device of  claim 2  wherein said first and second local read circuits comprise first and second switching devices for selectively coupling said first and second pairs of complementary local data read lines to said complementary global data read lines in response to said first and second read enable signals. 
     
     
       10. The integrated circuit device of  claim 9  wherein said first and second local write circuits comprise third and fourth switching devices for selectively coupling said first and second pairs of complementary local data write lines to said complementary global data write lines in response to said first and second write enable signals. 
     
     
       11. The integrated circuit device of  claim 10  wherein said first, second, third and fourth switching devices comprise MOS transistors. 
     
     
       12. The integrated circuit device of  claim 11  wherein said MOS transistors comprise N-channel transistors.