Inventor

WANG CHAO-HSIUNG

TW130 patents

⚠️ This page may combine multiple inventors who share the name “WANG CHAO-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG CHAO-HSIUNG

TAIWAN SEMICONDUCTOR MFG

FinFET device and method of manufacturing same

Phase change memory device and method of manufacture thereof

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Method for dicing semiconductor wafers

Isolation structure of fin field effect transistor

FinFET with buried insulator layer and method for forming

Fin structure of semiconductor device

Method and system for magnetic shielding in semiconductor integrated circuit

Structure for a multiple-gate FET device and a method for its fabrication

MRAM arrays and methods for writing and reading magnetic memory devices

Strained silicon layer semiconductor product employing strained insulator layer

Relaxed silicon germanium substrate with low defect density

MRAM arrays and methods for writing and reading magnetic memory devices

Method of forming a low voltage drive ferroelectric capacitor

Gate contact structure for FinFET

FinFET with dummy gate on non-recessed shallow trench isolation (STI)

Metal gate and gate contact structure for FinFET

Contact etch stop layers of a field effect transistor

Multi-fin device and method of making same

FinFETs with gradient germanium-containing channels

Structure and method for vertical tunneling field effect transistor with leveled source and drain

Metal gate and gate contact structure for FinFET

Relaxed silicon germanium substrate with low defect density

Magnetic shielding for magnetically sensitive semiconductor devices

Semiconductor structure and method for integrating SOI devices and bulk devices

Strained channel on insulator device

Interconnect structure with polygon cell structures

Method for forming a multi-layer seed layer for improved Cu ECP

Systems and methods for annealing semiconductor structures

Write line design in MRAM

Copper wiring with high temperature superconductor (HTS) layer

Multiple width and/or thickness write line in MRAM

TAIWAN SEMICONDUCTOR MFG CO LTD

Stacked grid design for improved optical performance and isolation

Fin spacer protected source and drain regions in FinFETs

Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture

Strained channel of gate-all-around transistor

Dielectric grid bottom profile for light focusing

FinFET structure and method for fabricating the same

Method of forming a Fin structure of semiconductor device

Systems and methods for annealing semiconductor structures

Structure and method for vertical tunneling field effect transistor with leveled source and drain

Fin spacer protected source and drain regions in FinFETs

LIU CHI-WEN

FinFET device and method of manufacturing same

Multi-fin device and method of making same

FinFET device and method of manufacturing same

LIU CHI WEN

3D capacitor and method of manufacturing same

TSMC SOLID STATE LIGHTING LTD

Single phosphor layer photonic device for generating white light or color lights

HUANG HSIN-CHIEH

Single phosphor layer photonic device for generating white light or color lights

CHEN HUNG-WEI

Structure for a multiple-gate FET device and a method for its fabrication

TAIWAN SEMICONDUCTOR MANUFACTORING COMPANY LTD

Fin spacer protected source and drain regions in FinFETs