Structure for a multiple-gate FET device and a method for its fabrication

Abstract

A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

What is claimed is: 
     
       1. A method for forming a semiconductor device, comprising:
 forming a hard mask layer on a semiconductor substrate;   patterning the hard mask layer to form a plurality of openings;   etching the substrate through the plurality of openings of the hard mask layer to form a plurality of trenches separating a plurality of semiconductor mesas, wherein each of the plurality of semiconductor mesas is formed to have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, and wherein each of the plurality of trenches is formed to have a top trench portion having a sidewall of the first slope and a bottom trench portion having a sidewall of the second slope, and wherein the first slope is different from the second slope;   partially filling the plurality of trenches with a dielectric material;   removing the hard mask layer; and   forming a plurality of multiple-gate features, each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the plurality of semiconductor mesas.   
     
     
       2. The method of  claim 1  further comprising:
 performing a thermal oxidizing process on the plurality of semiconductor mesas to form a semiconductor oxide layer; and 
 removing the semiconductor oxide layer to narrow the plurality of semiconductor mesas before forming the plurality of multiple-gate features on the substrate. 
 
     
     
       3. The method of  claim 1  wherein the first slope ranges from about 90 degrees to about 85 degrees. 
     
     
       4. The method of  claim 1  wherein the second slope ranges from about 60 degrees to about 85 degrees. 
     
     
       5. The method of  claim 1  wherein the partially filling the plurality of trenches comprises substantially filling the plurality of bottom trench portions. 
     
     
       6. The method of  claim 1  wherein the partially filling the plurality of trenches comprises:
 substantially filling the plurality of both top and bottom trench portions to form a first group of shallow trench isolation (STI) features and a second group of STI features; 
 forming a photoresist layer patterned to cover the first group of STI features; and 
 recessing the second group of STI features such that the second group of STI features are substantially within the bottom trench portions. 
 
     
     
       7. The method of  claim 6  wherein the recessing comprises a reactive ion etching (RIE) process. 
     
     
       8. The method of  claim 1  wherein the partially filling the plurality of trenches comprises utilizing a high density plasma chemical vapor deposition (HDP-CVD) process. 
     
     
       9. The method of  claim 1  wherein the dielectric material comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low dielectric constant (K) materials, and combinations thereof. 
     
     
       10. The method of  claim 1  wherein the etching the substrate through the plurality of openings of the hard mask layer comprises using multiple processes. 
     
     
       11. The method of  claim 10  wherein the multiple processes comprise a method selected from the group consisting of dry etching, wet etching, and RIE. 
     
     
       12. The method of  claim 1  wherein the forming a hard mask layer comprises forming a silicon oxynitride layer. 
     
     
       13. The method of  claim 1  further comprising forming a pad layer on the substrate before forming the hard mask layer. 
     
     
       14. The method of  claim 13  wherein the pad layer comprises silicon oxide formed by a thermal oxidation process. 
     
     
       15. A method for forming a semiconductor device, comprising:
 forming a hard mask layer on a semiconductor substrate;   patterning the hard mask layer to form a plurality of openings;   etching the substrate through the plurality of openings to form a plurality of trenches separating a plurality of semiconductor mesas, wherein the plurality of semiconductor trenches are each defined by a top trench portion having a sidewall of a first slope and a bottom trench portion having a sidewall of a second slope, and each of the plurality of semiconductor mesas have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, and wherein the first slope is different from the second slope;   substantially filling the plurality of trenches to form first shallow trench isolation (STI) features in a first region and second STI features in a second region;   forming a photoresist layer patterned to cover the first STI features in the first region and leave a second STI features in the second region uncovered;   recessing the second STI features such that the second STI features are substantially within the bottom trench portions;   removing the patterned hard mask layer; and   forming a plurality of multiple-gate features on the substrate.   
     
     
       16. The method of  claim 15  wherein the recessing utilizes a reactive ion etching process. 
     
     
       17. The method of  claim 15  further comprising:
 performing a thermal oxidizing process on the plurality of top semiconductor mesas in the second region to form a semiconductor oxide layer; and 
 removing the semiconductor oxide layer. 
 
     
     
       18. A method for forming a semiconductor device, comprising:
 patterning a substrate to form a plurality of trenches;   partially filling the plurality of trenches with a dielectric material, resulting in a plurality of semiconductor mesas interposed by at least one of the plurality of trenches, wherein each of the plurality of semiconductor mesas is formed to have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, wherein each of the plurality of trenches has a top portion sidewall of a first slope and a bottom portion sidewall of a second slope, and wherein the first slope is different from the second slope; and   forming a plurality of gate electrodes on the substrate, each being in contact with a top surface and sidewalls of at least one of the plurality of semiconductor mesas.   
     
     
       19. The method of  claim 18  wherein the patterning a substrate comprises:
 forming a hard mask layer on the substrate; 
 patterning the hard mask layer to form a plurality of openings; and 
 etching the substrate through the plurality of openings of the hard mask layer to form the plurality of trenches. 
 
     
     
       20. A microelectronic product comprising:
 a semiconductor substrate;   a plurality of trenches formed in the semiconductor substrate, the plurality of trenches being partially filled with a dielectric material;   a plurality of mesas, wherein each of the plurality of mesas is formed between adjacent ones of the plurality of trenches, and further wherein each of the plurality of mesas comprises a top mesa and a bottom mesa, the top mesa having a sidewall of a first slope and the bottom mesa having a sidewall of a second slope different from the first slope, the sidewall of the top mesa and the sidewall of the bottom mesa being sidewalls of a same trench, the sidewall of the top mesa being indented from a top end of the sidewall of the bottom mesa; and   a plurality of multi-gate features comprising a gate dielectric material extending continuously from a sidewall of the top mesa of a first one of the plurality of mesas over and in contact with the top surface of the dielectric material in one of the plurality of trenches and onto a sidewall of a top mesa of a second one of the plurality of mesas, each of the plurality of multi-gate features being disposed over a top surface and sidewalls of a respective one of the plurality of mesas.   
     
     
       21. The microelectronic product of claim 20 wherein the first slope ranges from about 90 degrees to about 85 degrees. 
     
     
       22. The microelectronic product of claim 20 wherein the second slope ranges from about 60 degrees to about 85 degrees. 
     
     
       23. The microelectronic product of claim 20 wherein the plurality of mesas have at least two pre-selected crystal orientations, the at least two pre-selected crystal orientations being selected from the group consisting of crystal orientations (100), (110), and (111). 
     
     
       24. The microelectronic product of claim 20 wherein the bottom mesa has a thickness ranging from 200 nm to 1,000 nm. 
     
     
       25. The microelectronic product of claim 20 wherein the top mesa has a thickness ranging from 10 nm to 100 nm. 
     
     
       26. The microelectronic product of claim 20 wherein a thickness of one sidewall to another sidewall of the top mesa ranges from 5 nm to 100 nm. 
     
     
       27. The microelectronic product of claim 20 wherein the dielectric material comprises an oxide formed by high density plasma CVD (HDP-CVD). 
     
     
       28. The microelectronic product of claim 20 wherein the dielectric material comprises a material selected from the group consisting of fluorinated silicate glass (FSG), low dielectric constant (K) materials, and combinations thereof. 
     
     
       29. The microelectronic product of claim 20 wherein gate dielectric material comprises a high-k gate dielectric material. 
     
     
       30. The microelectronic product of claim 29 wherein the high-k gate dielectric material comprises metal oxide. 
     
     
       31. The microelectronic product of claim 29 wherein the high-k gate dielectric material comprises HfO 2 , ZrO 2 , HfSiON, HfSi x , HfSi x N y , HfAlO 2 , or NiSi x . 
     
     
       32. The microelectronic product of claim 29 wherein the high-k gate dielectric material is formed by Atomic Layer Deposition (ALD). 
     
     
       33. The microelectronic product of claim 20 wherein the plurality of multi-gate features comprises a metal gate electrode. 
     
     
       34. The microelectronic product of claim 33 wherein the metal gate electrode comprises titanium nitride, ruthenium, copper, or tungsten. 
     
     
       35. The microelectronic product of claim 33 wherein the metal gate electrode comprises nickel silicide. 
     
     
       36. The microelectronic product of claim 33 wherein the metal gate electrode comprises metal formed by Atomic Layer Deposition (ALD).