Inventor

AHMED SHIBLY S

US45 patents

⚠️ This page may combine multiple inventors who share the name “AHMED SHIBLY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AHMED SHIBLY S

ADVANCED MICRO DEVICES INC

Semiconductor device having a U-shaped gate structure

Damascene gate process with sacrificial oxide in semiconductor devices

Double gate semiconductor device having separate gates

Reversed T-shaped FinFET

Method for forming a tri-gate MOSFET

Multi-step chemical mechanical polishing of a gate area in a FinFET

Method for forming a fin in a finFET device

Systems and methods for forming dense n-channel and p-channel fins using shadow implanting

Sacrificial oxide for minimizing box undercut in damascene FinFET

Isolated FinFET P-channel/N-channel transistor pair

Damascene finfet gate with selective metal interdiffusion

Narrow fins by oxidation in double-gate finfet

Method using planarizing gate material to improve gate critical dimension in semiconductor devices

Double gate semiconductor device having a metal gate

Narrow-body damascene tri-gate FinFET

Narrow body raised source/drain metal gate MOSFET

Self aligned damascene gate

Damascene gate semiconductor processing with local thinning of channel region

Semiconductor device having a gate structure surrounding a fin

Non-volatile memory device

Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages

System and method for forming stacked fin structure using metal-induced-crystallization

Additional gate control for a double-gate MOSFET

Dual silicon layer for chemical mechanical polishing planarization

Merged FinFET P-channel/N-channel pair

Reversed T-shaped finfet

Systems and methods for forming multiple fin structures using metal-induced-crystallization

Selective channel implantation for forming semiconductor devices with different threshold voltages

Damascene tri-gate FinFET

Semiconductor device with fully silicided source/drain and damascence metal gate

Method of manufacturing a semiconductor device having a fin structure

Multi-step chemical mechanical polishing of a gate area in a FinFET

Varying carrier mobility in semiconductor devices to achieve overall design goals

Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices

Dual silicon layer for chemical mechanical polishing planarization

Dual silicon layer for chemical mechanical polishing planarization

Source and drain protection and stringer-free gate formation in semiconductor devices

Formation of semiconductor devices to achieve &lt;100&gt; channel orientation

GLOBALFOUNDRIES US INC

Input buffer with hysteresis-integrated voltage protection devices and receiver incorporating the input buffer

Low power power-up reset output driver

YU BIN

Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin

LIN CHUAN

Controlling the latchup effect

CYPRESS SEMICONDUCTOR CORP

Controlling the latchup effect

SPANSION LLC

Junction leakage suppression in memory devices

AHMED SHIBLY S

Junction leakage suppression in memory devices

Formation of semiconductor devices to achieve <100> channel orientation