Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices

Abstract

A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

1. A method of manufacturing a semiconductor device, comprising:
 forming a fin structure on an insulator; 
 depositing a gate material over the fin structure; 
 forming a sacrificial material over the gate material, wherein the sacrificial material includes an oxide; 
 planarizing the sacrificial material; 
 depositing an antireflective coating on the planarized sacrificial material; and 
 forming a gate structure from the gate material. 
 
   
   
     2. The method of  claim 1 , wherein the forming a fin structure includes:
 depositing a dielectric layer on a silicon layer, and 
 etching the dielectric layer and the silicon layer to define the fin structure, the fin structure including a silicon portion and a dielectric cap. 
 
   
   
     3. The method of  claim 1 , wherein the depositing a gate material includes:
 depositing polysilicon over the fin structure. 
 
   
   
     4. The method of  claim 3 , wherein the depositing a gate material further includes:
 depositing the polysilicon with a uniform thickness around the fin structure. 
 
   
   
     5. The method of  claim 1 , wherein the forming a sacrificial material includes:
 forming an oxide layer over the gate material. 
 
   
   
     6. The method of  claim 1 , wherein the planarizing includes:
 polishing a top surface of the sacrificial material by chemical mechanical polishing. 
 
   
   
     7. The method of  claim 1 , wherein the forming a gate structure includes:
 depositing a photoresist layer over the antireflective coating, and 
 patterning the photoresist layer to define the gate structure. 
 
   
   
     8. The method of  claim 7 , wherein the forming a gate structure further includes:
 selectively etching the photoresist layer, the sacrificial material, and the gate material to form the gate structure. 
 
   
   
     9. The method of  claim 1 , further comprising:
 removing the sacrificial material remaining on the gate structure. 
 
   
   
     10. The method of  claim 1 , wherein a smallest feature size of the gate structure is less than or equal to about 50 nm.