Inventor

BHATTACHARYA DIPANKAR

US47 patents

⚠️ This page may combine multiple inventors who share the name “BHATTACHARYA DIPANKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHATTACHARYA DIPANKAR

AGERE SYSTEMS INC

Differential buffer circuit with reduced output common mode variation

Self-bypassing voltage level translator circuit

Reliability comparator with hysteresis

Voltage translator circuit for a mixed voltage circuit

Power pin to power pin electro-static discharge (ESD) clamp

Electrostatic discharge protection in a semiconductor device

Buffer circuit with enhanced overvoltage protection

Buffer circuit with multiple voltage range

Floating well circuit having enhanced latch-up performance

Overvoltage tolerant input buffer

Enhanced output impedance compensation

Buffer circuit having multiplexed voltage level translation

Voltage level translator circuit with wide supply voltage range

Voltage level translator circuit

Programmable reset signal that is independent of supply voltage ramp rate

Semiconductor resistance compensation with enhanced efficiency

Semiconductor resistor

Multiple voltage level detection circuit

Method and apparatus for improving reliability of an integrated circuit having multiple power domains

Circuit having enhanced input signal range

Reference compensation circuit

Circuit for selectively bypassing a capacitive element

Multiple-mode compensated buffer circuit

Comparator circuit having reduced pulse width distortion

OPTI INC

Bus synchronization apparatus and method

Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system

Method and apparatus for arbitrating requests at two or more levels of priority using a single request line

System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction

Programmable hold delay

Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority

Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system

CISCO TECH INC

Unbiased token bucket

Generating and merging lookup results to apply multiple features

Method and system for providing redundancy within a network element

Aligning data in a wide, high-speed, source synchronous parallel link

High-speed memory for use in networking systems

Generating and merging lookup results to apply multiple features

BHATTACHARYA DIPANKAR

Voltage level translator circuit

Impedance compensation in a buffer circuit

Superconducting current source system

Pulse selector system

Electrostatic discharge protection circuit

Hybrid impedance compensation in a buffer circuit

LSI CORP

I/O buffer with low voltage semiconductor devices

Mode latching buffer circuit

Bias circuit scheme for improved reliability in high voltage supply with low voltage device

(unassigned)

Distriburted QoS policing system and method