Reference compensation circuit

Abstract

A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.

1. A compensation circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device, the reference circuit being configured to provide the first and second reference signals as separate and independent outputs; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively. 
 
   
   
     2. A compensation circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively; 
 wherein the reference circuit is configured for receiving a control signal, the reference circuit being operative in at least one of a first mode and a second mode in response to the control signal, wherein in the first mode the reference circuit generates the first reference signal, and in the second mode the reference circuit generates the second reference signal. 
 
   
   
     3. A compensation circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively; 
 wherein the reference circuit comprises an NMOS compensation portion and a PMOS compensation portion, the reference circuit being selectively operable in at least one of a first mode and a second mode, wherein in the first mode the NMOS compensation portion generates the first reference signal, and in the second mode the PMOS compensation portion generates the second reference signal. 
 
   
   
     4. The circuit of  claim 3 , wherein the reference circuit is configured such that when the reference circuit is operative in the first mode, the NMOS compensation portion is enabled and the PMOS compensation portion is disabled, and when the reference circuit is operative in the second mode, the PMOS compensation portion is enabled and the NMOS compensation portion is disabled. 
   
   
     5. The circuit of  claim 3 , wherein the reference is further operative in a third mode, the reference circuit being configured such that when the reference circuit is operative in the third mode, the NMOS compensation portion and the PMOS compensation portion are disabled. 
   
   
     6. A compensation circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively; 
 wherein the reference circuit comprises an NMOS compensation portion and a PMOS compensation portion, 
 the NMOS compensation portion comprising:
 the reference NMOS device including a drain terminal, a gate terminal and a source terminal; and 
 a current mirror connected to the drain terminal of the NMOS reference device at a first terminal and being connected to an output of the reference circuit at a second terminal; and 
 
 the PMOS compensation portion comprising:
 the reference PMOS device including a drain terminal, a gate terminal and a source terminal; 
 a first current mirror connected to the drain terminal of the reference PMOS device at a first terminal; and 
 a second current mirror connected to a second terminal of the first current mirror at a first terminal and being connected to the output of the reference circuit at a second terminal; 
 
 wherein the reference circuit is selectively operable in at least one of a first mode and a second mode, the NMOS compensation portion generating the first reference signal in the first mode, and the PMOS compensation portion generating the second reference signal in the second mode. 
 
   
   
     7. A compensation circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively; 
 wherein the reference circuit comprises an NMOS compensation portion and a PMOS compensation portion, the NMOS compensation portion including the reference NMOS device and a first current mirror connected to the reference NMOS device, the PMOS compensation portion including the reference PMOS device, a second current mirror connected to the reference PMOS device and a third current mirror connected to the second current mirror, wherein each of at least one of the first, second and third current mirrors is configurable for receiving a control signal and for selectively disabling the corresponding current mirror in response to the control signal. 
 
   
   
     8. The circuit of  claim 2 , wherein at least one of the first and second reference signals comprises a reference voltage, the reference voltage level being selectively adjustable as a function of at least one resistor connected to the reference circuit. 
   
   
     9. The circuit of  claim 2 , wherein the control circuit comprises an analog-to-digital converter operative to receive the first and second reference signals and to convert the first and second reference signals to first and second digital output signals, respectively, the first digital output signal comprising a digital representation of at least one of the process, voltage and temperature characteristic of the reference NMOS device, the second digital output comprising a digital representation of at least one of the process, voltage and temperature characteristic of the reference PMOS device. 
   
   
     10. The circuit of  claim 9 , wherein the analog-to-digital converter is operative: (i) to receive the first and second reference signals from the reference circuit; (ii) to compare the reference signals against a predetermined set of signal levels; (iii) to generate a first and second plurality of digital bits, the first and second plurality of digital bits representing a state of the reference NMOS device and reference PMOS device, respectively, under a particular process, voltage and temperature condition; and (iv) to transmit the digital bits to the circuit to be compensated. 
   
   
     11. The circuit of  claim 9 , wherein the plurality of digital bits is transmitted to the circuit to be compensated in a serial manner. 
   
   
     12. The circuit of  claim 9 , wherein the plurality of digital bits is transmitted to the circuit to be compensated in a parallel manner. 
   
   
     13. The circuit of  claim 2 , wherein the control signal comprises a clock signal including at least a first level and a second level, the reference circuit being operative in the first mode during the first clock level and being operative in the second mode during the second clock level. 
   
   
     14. The circuit of  claim 13 , wherein a duration of the first and second clock levels are substantially equal to one another. 
   
   
     15. The circuit of  claim 13 , wherein a duration of the first and second clock levels are not equal to one another. 
   
   
     16. The circuit of  claim 2 , wherein at least one of the reference NMOS device and the reference PMOS device in the reference circuit is formed in close relative proximity to the at least one NMOS device and at least one PMOS device, respectively, in the circuit to be compensated. 
   
   
     17. The circuit of  claim 2 , wherein at least one of the reference NMOS device and the reference PMOS device in the reference circuit is substantially matched to the at least one NMOS device and at least one PMOS device, respectively, in the circuit to be compensated. 
   
   
     18. A compensated buffer circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device, the reference circuit being configured to provide the first and second reference signals as separate and independent outputs; 
 an input/output buffer comprising an output stage including at least one NMOS device and at least one PMOS device; and 
 a control circuit connected to the reference circuit and to the input/output buffer, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the at least one NMOS device and the at least one PMOS device in the input/output buffer in response to the first and second reference signals, respectively. 
 
   
   
     19. A compensated buffer circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; 
 an input/output buffer comprising an output stage including at least one NMOS device and at least one PMOS device; and 
 a control circuit connected to the reference circuit and to the input/output buffer, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the at least one NMOS device and the at least one PMOS device in the input/output buffer in response to the first and second reference signals, respectively; 
 wherein the reference circuit is configured for receiving a control signal, the reference circuit being operative in at least one of a first mode and a second mode in response to the control signal, wherein in the first mode the reference circuit generates the first reference signal, and in the second mode the reference circuit generates the second reference signal. 
 
   
   
     20. The compensated buffer circuit of  claim 19 , wherein the control circuit comprises an analog-to-digital converter operative to receive the first and second reference signals and to convert the first and second reference signals to first and second digital output signals, respectively, the first digital output signal comprising a digital representation of at least one of the process, voltage and temperature characteristic of the reference NMOS device, the second digital output comprising a digital representation of at least one of the process, voltage and temperature characteristic of the reference PMOS device. 
   
   
     21. The compensated buffer circuit of  claim 20 , wherein the analog-to-digital converter is operative: (i) to receive the first and second reference signals from the reference circuit; (ii) to compare the reference signals against a predetermined set of signal levels; (iii) to generate a first and second plurality of digital bits, the first and second plurality of digital bits representing a state of the reference NMOS device and reference PMOS device, respectively, under a particular process, voltage and temperature condition; and (iv) to transmit the digital bits to the input/output buffer for operatively compensating the input/output buffer. 
   
   
     22. A compensated buffer circuit, comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; 
 an input/output buffer comprising an output stage including at least one NMOS device and at least one PMOS device; and 
 a control circuit connected to the reference circuit and to the input/output buffer, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the at least one NMOS device and the at least one PMOS device in the input/output buffer in response to the first and second reference signals, respectively; 
 wherein the reference circuit comprises an NMOS compensation portion and a PMOS compensation portion, the reference circuit being selectively operable in at least one of a first mode and a second mode, wherein in the first mode the NMOS compensation portion generates the first reference signal, and in the second mode the PMOS compensation portion generates the second reference signal. 
 
   
   
     23. An integrated circuit device including at least one compensation circuit, the at least one compensation circuit comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; and 
 a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively; 
 wherein the reference circuit is configured for receiving a control signal, the reference circuit being operative in at least one of a first mode and a second mode in response to the control signal, wherein in the first mode the reference circuit generates the first reference signal, and in the second mode the reference circuit generates the second reference signal. 
 
   
   
     24. An integrated circuit device including at least one compensated buffer circuit, the at least one compensated buffer circuit comprising:
 a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device; 
 an input/output buffer comprising an output stage including at least one NMOS device and at least one PMOS device; and 
 a control circuit connected to the reference circuit and to the input/output buffer, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the at least one NMOS device and the at least one PMOS device in the input/output buffer in response to the first and second reference signals, respectively; 
 wherein the reference circuit is configured for receiving a control signal, the reference circuit being operative in at least one of a first mode and a second mode in response to the control signal, wherein in the first mode the reference circuit generates the first reference signal, and in the second mode the reference circuit generates the second reference signal. 
 
   
   
     25. The circuit of  claim 1 , wherein the separate and independent outputs are provided by one of: (i) a single output line, the first reference signal being supplied on the output line in a first mode of operation of the reference circuit and the second reference signal being supplied on the output line in a second mode of operation of the reference circuit; and (ii) separate output lines for each of the first and second reference signals.