Inventor · disambiguated record
Dipankar Bhattacharya
Also filed as: BHATTACHARYA DIPANKAR
47 granted patents·3 pending applications·1,016 citations·filing 1992–2021
98Inventor score
Top patents by PatentIndex Score
50 records- 0196US11476842B1Superconducting current source systemBHATTACHARYA DIPANKAR·Filed 2021·Granted Oct 18, 2022·6 cites·20 claims
- 0293US7106107B2Reliability comparator with hysteresisAGERE SYSTEMS INC·Filed 2005·Granted Sep 12, 2006·25 cites·20 claims
- 0392US7145364B2Self-bypassing voltage level translator circuitAGERE SYSTEMS INC·Filed 2005·Granted Dec 5, 2006·21 cites·20 claims
- 0491US7529070B2Power pin to power pin electro-static discharge (ESD) clampAGERE SYSTEMS INC·Filed 2005·Granted May 5, 2009·35 cites·25 claims
- 0590US7382168B2Buffer circuit with multiple voltage rangeAGERE SYSTEMS INC·Filed 2005·Granted Jun 3, 2008·20 cites·19 claims
- 0689US7248079B2Differential buffer circuit with reduced output common mode variationAGERE SYSTEMS INC·Filed 2005·Granted Jul 24, 2007·20 cites·21 claims
- 0789US6826150B1Distriburted QoS policing system and methodFiled 2001·Granted Nov 30, 2004·72 cites·60 claims
- 0888US7397279B2Voltage level translator circuit with wide supply voltage rangeAGERE SYSTEMS INC·Filed 2006·Granted Jul 8, 2008·19 cites·18 claims
- 0988US7276957B2Floating well circuit having enhanced latch-up performanceAGERE SYSTEMS INC·Filed 2005·Granted Oct 2, 2007·17 cites·20 claims
- 1088US5371880ABus synchronization apparatus and methodOPTI INC·Filed 1992·Granted Dec 6, 1994·126 cites·82 claims
- 1187US8159262B1Impedance compensation in a buffer circuitBHATTACHARYA DIPANKAR·Filed 2011·Granted Apr 17, 2012·10 cites·25 claims
- 1287US5469555AAdaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor systemOPTI INC·Filed 1992·Granted Nov 21, 1995·110 cites·14 claims
- 1386US7139928B1Method and system for providing redundancy within a network elementCISCO TECH INC·Filed 2002·Granted Nov 21, 2006·46 cites·51 claims
- 1485US8536925B2Voltage level translator circuitBHATTACHARYA DIPANKAR·Filed 2008·Granted Sep 17, 2013·14 cites·20 claims
- 1585US7936209B2I/O buffer with low voltage semiconductor devicesLSI CORP·Filed 2009·Granted May 3, 2011·14 cites·14 claims
- 1684US7498860B2Buffer circuit having multiplexed voltage level translationAGERE SYSTEMS INC·Filed 2007·Granted Mar 3, 2009·13 cites·18 claims
- 1783US7057545B1Semiconductor resistance compensation with enhanced efficiencyAGERE SYSTEMS INC·Filed 2005·Granted Jun 6, 2006·10 cites·20 claims
- 1882US7430100B2Buffer circuit with enhanced overvoltage protectionAGERE SYSTEMS INC·Filed 2005·Granted Sep 30, 2008·12 cites·14 claims
- 1982US7369489B1Unbiased token bucketCISCO TECH INC·Filed 2002·Granted May 6, 2008·40 cites·97 claims
- 2082US7177978B2Generating and merging lookup results to apply multiple featuresCISCO TECH INC·Filed 2003·Granted Feb 13, 2007·32 cites·20 claims
- 2181US7551020B2Enhanced output impedance compensationAGERE SYSTEMS INC·Filed 2007·Granted Jun 23, 2009·10 cites·20 claims
- 2280US11342920B1Pulse selector systemBHATTACHARYA DIPANKAR·Filed 2021·Granted May 24, 2022·1 cites·20 claims
- 2380US6774698B1Voltage translator circuit for a mixed voltage circuitAGERE SYSTEMS INC·Filed 2003·Granted Aug 10, 2004·22 cites·26 claims
- 2475US8362803B2Mode latching buffer circuitLSI CORP·Filed 2011·Granted Jan 29, 2013·5 cites·21 claims
- 2575US7098694B2Overvoltage tolerant input bufferAGERE SYSTEMS INC·Filed 2004·Granted Aug 29, 2006·16 cites·19 claims
- 2675US7068074B2Voltage level translator circuitAGERE SYSTEMS INC·Filed 2004·Granted Jun 27, 2006·17 cites·20 claims
- 2774US7350020B2Generating and merging lookup results to apply multiple featuresCISCO TECH INC·Filed 2006·Granted Mar 25, 2008·5 cites·26 claims
- 2874US5805905AMethod and apparatus for arbitrating requests at two or more levels of priority using a single request lineOPTI INC·Filed 1995·Granted Sep 8, 1998·56 cites·69 claims
- 2973US7196561B2Programmable reset signal that is independent of supply voltage ramp rateAGERE SYSTEMS INC·Filed 2004·Granted Mar 27, 2007·17 cites·18 claims
- 3070US7511550B2Method and apparatus for improving reliability of an integrated circuit having multiple power domainsAGERE SYSTEMS INC·Filed 2006·Granted Mar 31, 2009·4 cites·20 claims
- 3169US8089739B2Electrostatic discharge protection circuitBHATTACHARYA DIPANKAR·Filed 2007·Granted Jan 3, 2012·4 cites·20 claims
- 3267US8598941B2Hybrid impedance compensation in a buffer circuitBHATTACHARYA DIPANKAR·Filed 2011·Granted Dec 3, 2013·4 cites·20 claims
- 3367US7720107B2Aligning data in a wide, high-speed, source synchronous parallel linkCISCO TECH INC·Filed 2004·Granted May 18, 2010·15 cites·6 claims
- 3466US7495873B2Electrostatic discharge protection in a semiconductor deviceAGERE SYSTEMS INC·Filed 2004·Granted Feb 24, 2009·12 cites·20 claims
- 3566US7047385B1High-speed memory for use in networking systemsCISCO TECH INC·Filed 2003·Granted May 16, 2006·18 cites·9 claims
- 3664US7432762B2Circuit having enhanced input signal rangeAGERE SYSTEMS INC·Filed 2006·Granted Oct 7, 2008·5 cites·20 claims
- 3763US5918072ASystem for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transactionOPTI INC·Filed 1995·Granted Jun 29, 1999·41 cites·30 claims
- 3859US7034653B2Semiconductor resistorAGERE SYSTEMS INC·Filed 2004·Granted Apr 25, 2006·9 cites·17 claims
- 3958US5463759AAdaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor systemOPTI INC·Filed 1995·Granted Oct 31, 1995·29 cites·11 claims
- 4055US6992489B2Multiple voltage level detection circuitAGERE SYSTEMS INC·Filed 2004·Granted Jan 31, 2006·7 cites·22 claims
- 4153US5448742AMethod and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priorityOPTI INC·Filed 1992·Granted Sep 5, 1995·24 cites·51 claims
- 4252US5577214AProgrammable hold delayOPTI INC·Filed 1995·Granted Nov 19, 1996·26 cites·14 claims
- 4350US7529071B2Circuit for selectively bypassing a capacitive elementAGERE SYSTEMS INC·Filed 2006·Granted May 5, 2009·1 cites·19 claims
- 4448US7902904B2Bias circuit scheme for improved reliability in high voltage supply with low voltage deviceLSI CORP·Filed 2008·Granted Mar 8, 2011·1 cites·19 claims
- 4546US7642807B2Multiple-mode compensated buffer circuitAGERE SYSTEMS INC·Filed 2007·Granted Jan 5, 2010·1 cites·21 claims
- 4643US7218169B2Reference compensation circuitAGERE SYSTEMS INC·Filed 2003·Granted May 15, 2007·4 cites·25 claims
- 4738US7391825B2Comparator circuit having reduced pulse width distortionAGERE SYSTEMS INC·Filed 2005·Granted Jun 24, 2008·0 cites·20 claims
- 4834US2005270065A1Coms buffer having higher and lower voltage operationBHATTACHARYA DIPANKAR·Filed 2004·Application pending·0 cites
- 4933US2006066381A1Voltage level translator circuit with feedbackBHATTACHARYA DIPANKAR·Filed 2004·Application pending·0 cites
- 5033US2006145749A1Bias circuit having reduced power-up delayBHATTACHARYA DIPANKAR·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →