Inventor · disambiguated record
John C. Kriz
Also filed as: KRIZ JOHN · KRIZ JOHN C · KRIZ JOHN CHRISTOPHER
40 granted patents·3 pending applications·501 citations·filing 1990–2011
98Inventor score
Top patents by PatentIndex Score
43 records- 0193US7106107B2Reliability comparator with hysteresisAGERE SYSTEMS INC·Filed 2005·Granted Sep 12, 2006·25 cites·20 claims
- 0292US7145364B2Self-bypassing voltage level translator circuitAGERE SYSTEMS INC·Filed 2005·Granted Dec 5, 2006·21 cites·20 claims
- 0391US7529070B2Power pin to power pin electro-static discharge (ESD) clampAGERE SYSTEMS INC·Filed 2005·Granted May 5, 2009·35 cites·25 claims
- 0490US7382168B2Buffer circuit with multiple voltage rangeAGERE SYSTEMS INC·Filed 2005·Granted Jun 3, 2008·20 cites·19 claims
- 0589US7248079B2Differential buffer circuit with reduced output common mode variationAGERE SYSTEMS INC·Filed 2005·Granted Jul 24, 2007·20 cites·21 claims
- 0688US7397279B2Voltage level translator circuit with wide supply voltage rangeAGERE SYSTEMS INC·Filed 2006·Granted Jul 8, 2008·19 cites·18 claims
- 0788US7276957B2Floating well circuit having enhanced latch-up performanceAGERE SYSTEMS INC·Filed 2005·Granted Oct 2, 2007·17 cites·20 claims
- 0887US8159262B1Impedance compensation in a buffer circuitBHATTACHARYA DIPANKAR·Filed 2011·Granted Apr 17, 2012·10 cites·25 claims
- 0985US8536925B2Voltage level translator circuitBHATTACHARYA DIPANKAR·Filed 2008·Granted Sep 17, 2013·14 cites·20 claims
- 1085US7936209B2I/O buffer with low voltage semiconductor devicesLSI CORP·Filed 2009·Granted May 3, 2011·14 cites·14 claims
- 1185US5017807AOutput buffer having capacitive drive shunt for reduced noiseAT & T BELL LAB·Filed 1990·Granted May 21, 1991·56 cites·8 claims
- 1284US7498860B2Buffer circuit having multiplexed voltage level translationAGERE SYSTEMS INC·Filed 2007·Granted Mar 3, 2009·13 cites·18 claims
- 1384US7170324B2Output buffer with selectable slew rateAGERE SYSTEMS INC·Filed 2004·Granted Jan 30, 2007·31 cites·19 claims
- 1483US7057545B1Semiconductor resistance compensation with enhanced efficiencyAGERE SYSTEMS INC·Filed 2005·Granted Jun 6, 2006·10 cites·20 claims
- 1582US7430100B2Buffer circuit with enhanced overvoltage protectionAGERE SYSTEMS INC·Filed 2005·Granted Sep 30, 2008·12 cites·14 claims
- 1681US7551020B2Enhanced output impedance compensationAGERE SYSTEMS INC·Filed 2007·Granted Jun 23, 2009·10 cites·20 claims
- 1780US6774698B1Voltage translator circuit for a mixed voltage circuitAGERE SYSTEMS INC·Filed 2003·Granted Aug 10, 2004·22 cites·26 claims
- 1879US8441281B2Current-mode logic buffer with enhanced output swingKOTHANDARAMAN MAKESHWAR·Filed 2011·Granted May 14, 2013·6 cites·21 claims
- 1976US6259295B1Variable phase shifting clock generatorAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jul 10, 2001·33 cites·9 claims
- 2075US8362803B2Mode latching buffer circuitLSI CORP·Filed 2011·Granted Jan 29, 2013·5 cites·21 claims
- 2175US7098694B2Overvoltage tolerant input bufferAGERE SYSTEMS INC·Filed 2004·Granted Aug 29, 2006·16 cites·19 claims
- 2275US7068074B2Voltage level translator circuitAGERE SYSTEMS INC·Filed 2004·Granted Jun 27, 2006·17 cites·20 claims
- 2373US7196561B2Programmable reset signal that is independent of supply voltage ramp rateAGERE SYSTEMS INC·Filed 2004·Granted Mar 27, 2007·17 cites·18 claims
- 2470US7511550B2Method and apparatus for improving reliability of an integrated circuit having multiple power domainsAGERE SYSTEMS INC·Filed 2006·Granted Mar 31, 2009·4 cites·20 claims
- 2569US8089739B2Electrostatic discharge protection circuitBHATTACHARYA DIPANKAR·Filed 2007·Granted Jan 3, 2012·4 cites·20 claims
- 2667US8598941B2Hybrid impedance compensation in a buffer circuitBHATTACHARYA DIPANKAR·Filed 2011·Granted Dec 3, 2013·4 cites·20 claims
- 2766US7495873B2Electrostatic discharge protection in a semiconductor deviceAGERE SYSTEMS INC·Filed 2004·Granted Feb 24, 2009·12 cites·20 claims
- 2864US7432762B2Circuit having enhanced input signal rangeAGERE SYSTEMS INC·Filed 2006·Granted Oct 7, 2008·5 cites·20 claims
- 2959US7034653B2Semiconductor resistorAGERE SYSTEMS INC·Filed 2004·Granted Apr 25, 2006·9 cites·17 claims
- 3057US7271614B2Buffer circuit with current limitingAGERE SYSTEMS INC·Filed 2005·Granted Sep 18, 2007·3 cites·20 claims
- 3155US6992489B2Multiple voltage level detection circuitAGERE SYSTEMS INC·Filed 2004·Granted Jan 31, 2006·7 cites·22 claims
- 3251US7869300B2Memory device control for self-refresh modeLSI CORP·Filed 2009·Granted Jan 11, 2011·3 cites·20 claims
- 3350US7529071B2Circuit for selectively bypassing a capacitive elementAGERE SYSTEMS INC·Filed 2006·Granted May 5, 2009·1 cites·19 claims
- 3448US7902904B2Bias circuit scheme for improved reliability in high voltage supply with low voltage deviceLSI CORP·Filed 2008·Granted Mar 8, 2011·1 cites·19 claims
- 3546US7876132B1Floating well circuit operable in a failsafe condition and a tolerant conditionLSI CORP·Filed 2009·Granted Jan 25, 2011·0 cites·20 claims
- 3646US7642807B2Multiple-mode compensated buffer circuitAGERE SYSTEMS INC·Filed 2007·Granted Jan 5, 2010·1 cites·21 claims
- 3745US2011102046A1Interfacing between differing voltage level requirements in an integrated circuit systemKUMAR PANKAJ·Filed 2009·Application pending·0 cites
- 3843US8130030B2Interfacing between differing voltage level requirements in an integrated circuit systemKUMAR PANKAJ·Filed 2009·Granted Mar 6, 2012·0 cites·20 claims
- 3943US8125267B2Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operationKUMAR PANKAJ·Filed 2010·Granted Feb 28, 2012·0 cites·21 claims
- 4043US7218169B2Reference compensation circuitAGERE SYSTEMS INC·Filed 2003·Granted May 15, 2007·4 cites·25 claims
- 4138US7391825B2Comparator circuit having reduced pulse width distortionAGERE SYSTEMS INC·Filed 2005·Granted Jun 24, 2008·0 cites·20 claims
- 4233US2006066381A1Voltage level translator circuit with feedbackBHATTACHARYA DIPANKAR·Filed 2004·Application pending·0 cites
- 4333US2006145749A1Bias circuit having reduced power-up delayBHATTACHARYA DIPANKAR·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →