Inventor

BAINS KULJIT S

US179 patents

⚠️ This page may combine multiple inventors who share the name “BAINS KULJIT S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAINS KULJIT S

INTEL CORP

Row hammer monitoring based on stored row hammer threshold value

Row hammer monitoring based on stored row hammer threshold value

Row hammer refresh command

Row hammer monitoring based on stored row hammer threshold value

Mapping a physical address differently to different memory devices in a group

Row hammer refresh command

Row hammer refresh command

Distributed row hammer tracking

Method, apparatus and system for responding to a row hammer event

Method and apparatus to counter mismatched burst lengths

Logical relocation of memory based on memory device type

Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations

Memory device having error checking and correction

Method and apparatus for providing debug functionality in a buffered memory channel

Internal error checking and correction (ECC) with extra system bits

Memory device error check and scrub mode and error transparency

Memory device error check and scrub mode and error transparency

On-die termination control without a dedicated pin in a multi-rank system

Programmable on-die termination timing in a multi-rank system

Memory device check bit read mode

Memory device on-die error checking and correcting code

Method, apparatus and system for responding to a row hammer event

Row hammer monitoring based on stored row hammer threshold value

Reliability, availability, and serviceability in a memory device

Method and apparatus for automatically selecting CPU clock frequency multiplier

Identifying and accessing individual memory devices in a memory channel

Method and apparatus for providing debug functionality in a buffered memory channel

Memory buffer device integrating refresh logic

Low load host/PCI bus bridge

Method and apparatus for latching data from a memory resource at a datapath unit

Method and apparatus providing fast access to a shared resource on a computer bus

Read retry to selectively disable on-die ECC

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Programmable data pattern for repeated writes to memory

Directed per bank refresh command

Techniques to access or operate a dual in-line memory module via multiple data channels

Validation of memory on-die error correction code

Common die implementation for memory devices with independent interface paths

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Techniques for a write zero operation

Apparatus, method and system for memory device access with a multi-cycle command

Directed per bank refresh command

BAINS KULJIT S

Row hammer refresh command

Method and system for error management in a memory device

Fast exit from self-refresh state of a memory device

Systems, methods, and apparatuses to save memory self-refresh power

MCCALL JAMES A

Methods and apparatuses for dynamic memory termination

Method and apparatus for dynamic memory termination

GREENFIELD ZVIKA

Row hammer condition monitoring

MACWILLIAMS PETER

Identifying and accessing individual memory devices in a memory channel