Inventor

SAULNIER NICOLE A

US32 patents

⚠️ This page may combine multiple inventors who share the name “SAULNIER NICOLE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAULNIER NICOLE A

IBM

Self aligned pattern formation post spacer etchback in tight pitch configurations

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Self aligned pattern formation post spacer etchback in tight pitch configurations

Method and structure for cut material selection

Self aligned conductive lines with relaxed overlay

FinFET gate cut after dummy gate removal

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Enhanced self-alignment of vias for a semiconductor device

Self aligned pattern formation post spacer etchback in tight pitch configurations

Self aligned conductive lines

Method and structure for forming a replacement contact

Separate N and P fin etching for reduced CMOS device leakage

Interconnect structure having large self-aligned vias

Photoresist bridging defect removal by reverse tone weak developer

Photoresist bridging defect removal by reverse tone weak developer

Enhanced self-alignment of vias for asemiconductor device

Structure and method for equal substrate to channel height between N and P fin-FETs

Self aligned conductive lines with relaxed overlay

Self aligned conductive lines with relaxed overlay

Self aligned conductive lines

Vertical transport FET with two or more gate lengths

Separate N and P fin etching for reduced CMOS device leakage

Structure and method for equal substrate to channel height between N and P fin-FETs

TESSERA INC

FinFET gate cut after dummy gate removal

Self aligned pattern formation post spacer etchback in tight pitch configurations

FinFET gate cut after dummy gate removal

ST MICROELECTRONICS INC

Interconnect structure having large self-aligned vias

Interconnect structure having large self-aligned vias

TESSERA LLC

Self aligned pattern formation post spacer etchback in tight pitch configurations

Self aligned pattern formation post spacer etchback in tight pitch configurations

ADEIA SEMICONDUCTOR SOLUTIONS LLC

FinFET gate cut after dummy gate removal