Inventor

HEMPEL KLAUS

DE22 patents

⚠️ This page may combine multiple inventors who share the name “HEMPEL KLAUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEMPEL KLAUS

GLOBALFOUNDRIES INC

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

Short-channel NFET device

Short-channel nFET device

Integrated circuits and methods of forming the same with effective dummy gate cap removal

HEMPEL KLAUS

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology

Metal gate stack formation for replacement gate technology

High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology

BEYER SVEN

High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

LENSKI MARKUS

Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer

ADVANCED MICRO DEVICES INC

Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same

TRIYOSO DINA

Methods for fabricating integrated circuits with controlled P-channel threshold voltage

METZGER JOACHIM

Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition

VAN BENTUM RALF

Trench isolation structure having different stress

PRUEFER EKKEHARD

Drain/source extension structure of a field effect transistor with reduced boron diffusion

PRINDLE CHRIS M

Dry etch polysilicon removal for replacement gates