Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

Abstract

In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

1. A method, comprising:
 forming a first stress-inducing layer above a first gate electrode structure of a first transistor and a second stress-inducing layer above a second gate electrode structure of a second transistor, said first and second gate electrode structures comprising a gate insulation layer including a high-k dielectric material and a placeholder material formed above said high-k dielectric material, wherein said first stress-inducing layer comprises an internal stress that is different from said second stress-inducing layer; 
 forming a dielectric material above said first and second stress-inducing layers and above said first and second gate electrode structures; 
 planarizing said dielectric material formed above said first stress-inducing layer and said second stress-inducing layer so as to expose a portion of said first stress-inducing layer and a portion of said second stress-inducing layer; 
 implanting an implantation species into said dielectric material and said portions of said first and second stress-inducing layers after planarizing said dielectric material; and 
 removing material of said dielectric material and said first and second stress-inducing layers so as to expose a sacrificial material of said first and second gate electrode structures, said removed material comprising at least a portion of said implantation species. 
 
     
     
       2. The method of  claim 1 , wherein at least one of said first stress-inducing layer and said second stress-inducing layer comprises at least one of silicon nitride and a nitrogen-containing silicon carbide. 
     
     
       3. The method of  claim 1 , wherein said implantation species comprises at least one of carbon, silicon and germanium. 
     
     
       4. The method of  claim 1 , wherein said ion implantation process is performed by using xenon as an implantation species. 
     
     
       5. The method of  claim 1 , wherein removing material of said dielectric material and said first and second stress-inducing layers comprises performing a wet chemical etch process. 
     
     
       6. The method of  claim 5 , wherein said wet chemical etch process is performed by using at least one of hydrofluoric acid (HF) and sulphuric acid (H 3 PO 4 ). 
     
     
       7. The method of  claim 1 , wherein removing material of said dielectric material and said first and second stress-inducing layers comprises performing a planarization process. 
     
     
       8. The method of  claim 1 , wherein planarizing said dielectric material comprises performing a planarization process and using said first and second stress-inducing layers as stop layers for controlling said planarization process. 
     
     
       9. A method, comprising:
 forming a first gate electrode structure and a second gate electrode structure, each of said first and second gate electrode structures comprising a sacrificial material; 
 forming first and second stress inducing layers above said first and second gate electrode structures, respectively; 
 forming a dielectric material above said first and second stress-inducing layers; 
 planarizing said dielectric material so as to expose a portion of said first stress-inducing layer and a portion of said second stress-inducing layer; 
 implanting an implantation species into said dielectric material and at least said exposed portions of said first and second stress-inducing layers after planarizing said dielectric material; and 
 removing material of said dielectric material and said first and second stress-inducing layers so as to expose said sacrificial material of said first and second gate electrode structures, said removed material comprising at least a portion of said implantation species. 
 
     
     
       10. The method of  claim 9 , wherein removing said material comprises performing a wet chemical etch process. 
     
     
       11. The method of  claim 9 , wherein removing said material comprises performing a polishing process. 
     
     
       12. The method of  claim 9 , further comprising replacing at least one of said sacrificial material of said first or said second gate electrode structures with a metal-containing electrode material.