Inventor

COHEN GUY M

US171 patents

⚠️ This page may combine multiple inventors who share the name “COHEN GUY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COHEN GUY M

IBM

Method of forming vertical FET with nanowire channels and a silicided bottom contact

Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques

Mixed orientation and mixed material semiconductor-on-insulator wafer

Double-gate FET with planarized surfaces and self-aligned silicides

Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP)

Self-aligned double gate mosfet with separate gates

Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer

III-V nanowire FET with compositionally-graded channel and wide-bandgap core

Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates

Gate-all-around nanowire field effect transistors

Fast P-I-N photodetector with high responsitivity

Vertical Fet with nanowire channels and a silicided bottom contact

Monolithic high aspect ratio nano-size scanning probe microscope (SPM) tip formed by nanowire growth

Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates

Self-aligned gate MOSFET with separate gates

Double-gate fet with planarized surfaces and self-aligned silicides

Method for increasing the capacitance of a trench capacitor

Nanowire MOSFET with doped epitaxial contacts for source and drain

Self-aligned isolation double-gate FET

Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques

Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices

Integrated resistive processing unit to avoid abrupt set of RRAM and abrupt reset of PCM

Ultra-sonic self-cleaning system

Unmanned vehicle for servicing equipment

Automatic eradication of bio-related contaminants from handles

Protecting content displayed on a mobile device

III-V gate-all-around field effect transistor using aspect ratio trapping

Epitaxial growth techniques for reducing nanowire dimension and pitch

Protecting content displayed on a mobile device

Nanowire field effect transistor with inner and outer gates

Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

Self-aligned isolation double-gate FET

Method of fabricating strained Si SOI wafers

Multi-level ferroelectric field-effect transistor devices

BANGSARUNTIP SARUNYA

Contacts for nanowire field effect transistors

Planar and nanowire field effect transistors

Self-aligned contacts for nanowire field effect transistors

Nanowire field effect transistor device

Nanowire field effect transistor device

Nanowire field effect transistors

Generation of multiple diameter nanowire field effect transistors

Omega shaped nanowire field effect transistors

COHEN GUY M

Replacement contacts for all-around contacts

Replacement contacts for all-around contacts

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

Fast p-i-n photodetector with high responsitivity

GLOBALFOUNDRIES INC

Silicided nanowires for nanobridge weak links

DIMITRAKOPOULOS CHRISTOS D

Semiconductor chip with graphene based devices in an interconnect structure of the chip