Self-aligned contacts for nanowire field effect transistors

Abstract

A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
 forming a nanowire over a semiconductor substrate; 
 forming a gate structure around a portion of the nanowire; 
 forming a capping layer on the gate structure; 
 forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate; 
 forming a hardmask layer on the capping layer and the first spacer; 
 removing exposed portions of the nanowire; 
 epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region; 
 forming a silicide material in the epitaxially grown doped semiconductor material; 
 forming a conductive material on the source and drain regions by:
 depositing a first layer of conductive material on the substrate, the source and drain regions, and the hardmask layer; 
 removing a portion of the first layer of conductive material and the hardmask layer; 
 depositing a second layer of conductive material on the first layer of conductive material and the capping layer; 
 patterning a protective mask material on the second layer of conductive material; and 
 etching to define a contact in the source region, a contact in the drain region, and a contact in a gate region; and 
 
 forming an isolation region around the device. 
 
     
     
       2. The method of  claim 1 , wherein the method further includes forming a silicide material in the capping layer after removing the portion of the first layer of conductive material and the hardmask layer. 
     
     
       3. The method of  claim 1 , wherein the method further includes forming a second spacer adjacent to sidewalls of the first spacer, sidewalls of the hardmask layer, and around portions of nanowire extending from the gate after forming the hardmask layer on the capping layer and the first spacer. 
     
     
       4. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is an n-type doped material. 
     
     
       5. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is a p-type doped material. 
     
     
       6. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is silicon. 
     
     
       7. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is a SiGe alloy. 
     
     
       8. The method of  claim 1 , wherein the gate structure includes a silicon oxide layer disposed on the gate portion of the nanowire, a dielectric layer disposed on the silicon oxide layer, and a metal layer disposed on the dielectric layer. 
     
     
       9. The method of  claim 1 , wherein the gate structure is formed in circumferential layers surrounding the gate portion of the nanowire. 
     
     
       10. The method of  claim 1 , wherein the first spacer includes a nitride material. 
     
     
       11. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is an in-situ doped material. 
     
     
       12. The method of  claim 1 , wherein the epitaxially grown doped semiconductor material is uniformly doped. 
     
     
       13. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
 forming a nanowire over a semiconductor substrate; 
 forming a gate structure around a portion of the nanowire; 
 forming a capping layer on the gate structure; 
 forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate; 
 forming a hardmask layer on the capping layer and the first spacer; 
 removing exposed portions of the nanowire; 
 doping the exposed portions of the nanowire to form source and drain regions; 
 forming a silicide material in the source and drain regions of the exposed portions of the nanowire; 
 forming a conductive material on the source and drain regions by:
 removing the hardmask layer; 
 forming a silicide material in the capping layer; 
 depositing a first layer of conductive material on the substrate, the source and drain regions, and the silicide material in the capping layer; 
 removing a portion of the first layer of conductive material to expose the silicide material in the capping layer; 
 depositing a second layer of conductive material on the first layer of conductive material and the silicide material in the capping layer; 
 patterning a protective mask material on the second layer of conductive material; and 
 etching to define a contact in the source region, a contact in the drain region, and a contact in a gate region; and 
 
 forming an isolation region around the device. 
 
     
     
       14. The method of  claim 13 , wherein the method further includes forming a silicide material in the capping layer after removing the portion of the first layer of conductive material and the hardmask layer. 
     
     
       15. The method of  claim 13 , wherein the method further includes forming a second spacer adjacent to sidewalls of the first spacer, sidewalls of the hardmask layer, and around portions of nanowire extending from the gate after forming the hardmask layer on the capping layer and the first spacer. 
     
     
       16. A nanowire field effect transistor (FET) device including:
 a channel region including a silicon portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate structure disposed circumferentially around the silicon portion; 
 a polysilicon capping layer disposed on a substrate, the polysilicon capping layer having a silicide portion disposed on the gate structure; 
 a source region having a silicide portion, the source region including a first doped epi-silicon nanowire extension contacting the first distal end of the silicon portion; 
 a drain region having a silicide portion, the drain region including a second doped epi-silicon nanowire extension contacting the second distal end of the silicon portion; 
 a first conductive member contacting the silicide portion of the polysilicon capping layer and the substrate; 
 a second conductive member contacting the silicide portion of the source region; and 
 a third conductive member contacting the silicide portion of the drain region.