Inventor

BARTLEY GERALD K

US90 patents

⚠️ This page may combine multiple inventors who share the name “BARTLEY GERALD K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARTLEY GERALD K

IBM

Heatsink and package structures with fusible release layer

Integrated circuit chip package having configurable contacts and method for making the same

Integrated circuit chip package having configurable contacts and a removable connector

Capacitance-based microchip exploitation detection

Multi-level memory architecture with data prioritization

Method for personalizing integrated circuit devices

Residual material detection in backdrilled stubs

Residual material detection in backdrilled stubs

Environmental-based location monitoring

Residual material detection in backdrilled stubs

Structure for hub for supporting high capacity memory subsystem

Capacitance structures for defeating microchip tampering

Method and structure for dispensing chip underfill through an opening in the chip

Dynamic latency map for memory optimization

False connection for defeating microchip exploitation

Efficient memory usage in systems including volatile and high-density memories

Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance

Secure crypto module including electrical shorting security layers

Secure crypto module including electrical shorting security layers

Secure crypto module including optical glass security layer

Secure crypto module including electrical shorting security layers

Dynamic clock lane assignment for increased performance and security

Authentication using optically sensed relative position

Multiple active vertically aligned cores for three-dimensional chip stack

Multiple active vertically aligned cores for three-dimensional chip stack

Method and system for internal layer-layer thermal enhancement

Through-substrate via power gating and delivery bipolar transistor

Intelligent chip placement within a three-dimensional chip stack

Interconnect solder bumps for die testing

Structure for memory chip for high capacity memory subsystem supporting multiple speed bus

Structure and method of implementing power savings during addressing of DRAM architectures

Electrical connection management using a card

Secure crypto module including optical glass security layer

Flexible rework device

Techniques for providing switchable decoupling capacitors for an integrated circuit

BARTLEY GERALD K

Hybrid bonding techniques for multi-layer semiconductor stacks

Enhanced thermal management of 3-D stacked die packaging

Universal inter-layer interconnect for multi-layer semiconductor stacks

Through silicon via direct FET signal gating

Thermal enhancement for multi-layer semiconductor stacks

Hybrid bonding techniques for multi-layer semiconductor stacks

Three dimensional chip fabrication

Field-effect transistor and method of creating same

Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies

Power domain controller with gated through silicon via having FET with horizontal channel

Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks

Continuity check monitoring for microchip exploitation detection

Signal quality monitoring to defeat microchip exploitation

Resistance sensing for defeating microchip exploitation

Doped implant monitoring for microchip tamper detection