US10170578B2ActiveUtilityA1

Through-substrate via power gating and delivery bipolar transistor

70
Assignee: IBMPriority: May 31, 2017Filed: May 31, 2017Granted: Jan 1, 2019
Est. expiryMay 31, 2037(~10.9 yrs left)· nominal 20-yr term from priority
H10W 20/0245H10W 20/0234H10W 20/0242H10W 90/722H10W 90/724H10W 72/248H10W 72/252H10W 72/244H10W 20/20H10W 90/721H10W 20/42H01L 2924/1305H01L 2224/16221H01L 29/732H01L 29/0804H01L 24/16H01L 29/66234H10D 64/281H10D 64/01H10D 62/137H10D 10/461H10D 10/056H10D 10/052H10D 10/40H10D 10/01
70
PatentIndex Score
1
Cited by
16
References
5
Claims

Abstract

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor substrate, comprising:
 a through-substrate via (TSV) comprising:
 a sidewall insulator defining an outer boundary of the TSV, and 
 a bipolar junction transistor disposed within the sidewall insulator, the bipolar junction transistor comprising:
 a first semiconductor layer doped with a first-type of dopant, wherein the first semiconductor layer comprises a collector, 
 a second semiconductor layer doped with a second-type of dopant, wherein the second semiconductor layer comprises a base, and 
 a third semiconductor layer doped with the first-type of dopant, wherein the third semiconductor layer comprises an emitter, and wherein the first, second, and third semiconductor layers are arranged in the TSV to form one of: a PNP junction and an NPN junction, wherein the base is disposed between the collector and the emitter in the TSV, wherein a material of the collector forms an annular shape, wherein a base contact is disposed in a central opening of the annular shape, wherein the base contact comprises a conductive material that directly contacts the base in the second semiconductor layer. 
 
 
 
     
     
       2. The semiconductor substrate of  claim 1 , wherein the TSV extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate opposite the top surface, wherein the base contact and the collector are closer to the top surface than the emitter and wherein the emitter is closer to the bottom surface than the base contact and the collector. 
     
     
       3. The semiconductor substrate of  claim 1 , further comprising:
 a metal routing layer comprising routing traces electrically coupling the bipolar junction transistor to electrical components disposed in the semiconductor substrate that are outside of the sidewall insulator. 
 
     
     
       4. An assembly, comprising:
 a through-substrate via (TSV) extending through a semiconductor substrate, the TSV comprising:
 a sidewall insulator, and 
 a bipolar transistor disposed within the sidewall insulator, the bipolar transistor comprising:
 a first semiconductor layer doped with a first-type of dopant, 
 wherein the first semiconductor layer comprises a collector, 
 a second semiconductor layer doped with a second-type of dopant, wherein the second semiconductor layer comprises a base, and 
 a third semiconductor layer doped with the first-type of dopant, wherein the third semiconductor layer comprises an emitter; 
 a first substrate; and 
 a solder connection coupling a first end of the TSV to the first substrate, wherein the base is disposed between the collector and the emitter in the TSV, wherein a material of the collector forms an annular shape, wherein a base contact is disposed in a central opening of the annular shape, and wherein the base contact comprises a conductive material that directly contacts the base in the second semiconductor layer. 
 
 
 
     
     
       5. The assembly of  claim 4 , a metal routing layer disposed on the semiconductor substrate, wherein a second end of the TSV opposite the first end is electrically coupled to at least one routing trace in the metal routing layer.

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