P

Inventor

FANNING BLAISE B

US17 patents

Patents

17 patents
US6523092B1Feb 18, 2003

Cache line replacement policy enhancement to avoid memory page thrashing

INTEL CORP253 citations98
US6330639B1Dec 11, 2001

Method and apparatus for dynamically changing the sizes of pools that control the power consumption levels of memory devices

INTEL CORP100 citations96
US6968410B2Nov 22, 2005

Multi-threaded processing of system management interrupts

INTEL CORP21 citations92
US6918001B2Jul 12, 2005

Point-to-point busing and arrangement

INTEL CORP27 citations92
US6918060B2Jul 12, 2005

Bounding data transmission latency based upon link loading and arrangement

INTEL CORP32 citations92
US6650586B1Nov 18, 2003

Circuit and system for DRAM refresh with scoreboard methodology

INTEL CORP19 citations92
US6625695B2Sep 23, 2003

Cache line replacement policy enhancement to avoid memory page thrashing

INTEL CORP16 citations92
US6615308B1Sep 2, 2003

Method and apparatus for regulating write burst lengths

INTEL CORP40 citations92
US6880111B2Apr 12, 2005

Bounding data transmission latency based upon a data transmission event and arrangement

INTEL CORP16 citations84
US6604186B1Aug 5, 2003

Method for dynamically adjusting memory system paging policy

INTEL CORP15 citations84
US6467031B1Oct 15, 2002

Method and apparatus for reducing processor bus loading

INTEL CORP17 citations84
US7017008B2Mar 21, 2006

Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device

INTEL CORP7 citations73
US6904499B2Jun 7, 2005

Controlling cache memory in external chipset using processor

INTEL CORP7 citations73
US6684311B2Jan 27, 2004

Method and mechanism for common scheduling in a RDRAM system

INTEL CORP8 citations73
US6496894B1Dec 17, 2002

Method for enforcing device connection policies

INTEL CORP11 citations73
US7313653B2Dec 25, 2007

Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device

INTEL CORP2 citations62
US7213107B2May 1, 2007

Dedicated cache memory

INTEL CORP2 citations62