Inventor

ASADI MEYSAM

US55 patents

⚠️ This page may combine multiple inventors who share the name “ASADI MEYSAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASADI MEYSAM

SK HYNIX INC

Performance of a bit flipping (BF) decoder of an error correction system

Deep learning based regression framework for read thresholds in a NAND flash memory

Decoding codeword based on higher order information

Error mitigation scheme for bit-flipping decoders for irregular low-density parity-check codes

Hard error tracker and HRR dynamic reordering

Bit-flipping decoder and decoding method for irregular codes

On-the-fly scaling factor change for irregular LDPC codes

Exact ber reporting in the presence of CRC termination

Read retry threshold optimization systems and methods conditioned on previous reads

Oscillation detection and mitigation in bit-flipping decoders

Systems for adaptively determining read threshold voltage using meta information

Read threshold optimization systems and methods using model-less regression

Gaussian modeling for soft-read threshold estimation in non-volatile memory devices

Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes

Dynamic control of quasi-cyclic low-density parity-check bit-flipping decoder

Fast fail support for error correction in non-volatile memory

Error characteristic estimation for NAND flash

Reducing the latency of a syndrome-based quasi-cyclic decoder

Encoder for memory system and method thereof

Non-blocking chipkill recovery

Error correction based on asymmetric ratio

PV distribution variation detection and data reclaim policy

Soft decoding error prediction

Parameter estimation based on previous read attempts in memory devices

Quality-based dynamic scheduling LDPC decoder

Machine-learning based LLR generation without assist-read for early-stage soft decoding

Tracking read voltages in memory devices using deep neural networks

Method and system for fast column processing for highly irregular LDPC codes

System and method for history-based non-parametric channel information prediciton using a deep neural network

Min-sum decoder for row-irregular low density parity check codes

Read threshold estimation systems and methods using deep learning

Descrambler for memory systems and method thereof

Read threshold optimization systems and methods by multi-dimensional search

Memory system with low-latency read recovery and method of operating the memory system

Hardware implementations of a quasi-cyclic syndrome decoder

Quality of service (QoS) aware data storage decoder

Fast-converging soft bit-flipping decoder for low-density parity-check codes

Soft-input soft-output component code decoder for generalized low-density parity-check codes

Data recovery with enhanced super chip-kill recovery and method of operating such memory system

Compressing check node unit parameters in low-density parity-check codes in non-volatile memory devices

In-nand read threshold voltage search system and method

Min-sum decoding for irregular low-density parity check codes in memory devices

Machine-learning assisted decoder with asymmetric ratio tracking in non-volatile memory devices

Out-of-order bit-flipping decoders for non-volatile memory devices

Asymmetric bit errors in low-density parity-check codes for non-volatile memory devices

Error floor performance of a bit flipping decoder through identifying unreliable check nodes

Memory system with low-complexity decoding and method of operating such memory system

Memory system with error-reduction scheme for decoding and method of operating such memory system

SEAGATE TECHNOLOGY LLC

Capacitance coupling parameter estimation in flash memories

Capacitance coupling parameter estimation in flash memories