Inventor

STANDAERT THEODORUS E

US272 patents

⚠️ This page may combine multiple inventors who share the name “STANDAERT THEODORUS E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STANDAERT THEODORUS E

IBM

Replacement metal gate structures

Air-gap top spacer and self-aligned metal gate for vertical fets

Airgap formation between source/drain contacts and gates

Method and structure for forming gate contact above active area with trench silicide

Replacement metal gate structures

Structures and methods for embedded magnetic random access memory (MRAM) fabrication

Reduced tip-to-tip and via pitch at line end

Vertical transistor with a body contact for back-biasing

FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure

Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Precise control of vertical transistor gate length

Replacement metal gate structures

FinFET devices

FinFET devices

Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture

Gate stack integrated metal resistors

Method and structure for forming gate contact above active area with trench silicide

finFET isolation by selective cyclic etch

Bulk fin-field effect transistors with well defined isolation

Fin isolation in multi-gate field effect transistors

Bulk fin-field effect transistors with well defined isolation

Bulk fin-field effect transistors with well defined isolation

Uniform finFET gate height

Interconnect structure for integrated circuits having improved electromigration characteristics

Pillar-based memory hardmask smoothing and stress reduction

Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts

Bottom electrode for semiconductor memory device

Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture

Vertical transport FET devices having air gap top spacer

Method of forming via contact with resistance control

Replacement metal gate structures

Fin pitch scaling for high voltage devices and low voltage devices on the same wafer

Semiconductor structures with deep trench capacitor and methods of manufacture

Replacement metal gate structures

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Cut-very-last dual-EPI flow

Method for fabricating finFET with merged fins and vertical silicide

CHENG KANGGUO

Bulk fin-field effect transistors with well defined isolation

Bulk fin-field effect transistors with well defined isolation

MOS capacitors with a finfet process

ANDO TAKASHI

FinFET parasitic capacitance reduction using air gap

FinFET parasitic capacitance reduction using air gap

HORAK DAVID V

Method of forming replacement metal gate with borderless contact and structure thereof

TESSERA LLC

FinFET devices