Inventor

LICHTENAU CEDRIC

DE105 patents

⚠️ This page may combine multiple inventors who share the name “LICHTENAU CEDRIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LICHTENAU CEDRIC

IBM

Rapid character substring searching

Computerized methods for prefetching data based on machine learned sequences of memory addresses

Data conversion to/from selected data type with implied rounding mode

Normalization of a product on a datapath

Providing accurate time-based counters for scaling operating frequencies of microprocessors

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

Secure power-on reset engine

Data access protection for computer systems

Method and apparatus for on-the-fly minimum power state transition

Digit validation check control in instruction execution

Negative zero control in instruction execution

Method and apparatus for processing storage instructions

Performance-aware instruction scheduling

Chip testing with exclusive OR

Decimal scale and convert and split to hexadecimal floating point instruction

Logic built in self test circuitry for use in an integrated circuit with scan chains

Non-overlapping substring detection within a data element string

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

Multiply-add operations of binary numbers in an arithmetic unit

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Design-based weighting for logic built-in self-test

Clock dithering system and method during frequency scaling

Accelerator trustworthiness

Method and apparatus for dynamic system-level frequency scaling

Dynamic algorithm selection

Decision tree training and inference with mixed precision

Rounding hexadecimal floating point numbers using binary incrementors

Vector convert hexadecimal floating point to scaled decimal instruction

Vector string search instruction

Condition code anticipator for hexadecimal floating point

Fault-tolerant clock gating

Vector string search instruction

Method and apparatus for wiring multiple technology evaluation circuits

Computerized branch predictions and decisions

Computerized branch predictions and decisions

Selection of variable memory-access size

Time-base implementation for correcting accumulative error with chip frequency scaling

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Plausability-driven fault detection in result logic and condition codes for fast exact substring match

Rapid partial substring matching

Multiply-add operations of binary numbers in an arithmetic unit

System and method for synchronizing divide-by counters

Padding input data for artificial intelligence accelerators

Reducing power requirements and switching during logic built-in-self-test and scan test

Method and apparatus for on-the-fly minimum power state transition

Variable replacement by an artificial intelligence accelerator

Accelerating decision tree inferences based on complementary tensor operation sets

GLOBALFOUNDRIES INC

Electronic circuit having serial latch scan chains

BONSELS STEFAN

Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit