Inventor · disambiguated record
Mirem Hyuseinova
Also filed as: HYUSEINOVA MIREM
5 granted patents·3 pending applications·19 citations·filing 2011–2018
74Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0182US9280474B2Adaptive data prefetchingINTEL CORP·Filed 2013·Granted Mar 8, 2016·9 cites·21 claims
- 0276US9870209B2Instruction and logic for reducing data cache evictions in an out-of-order processorINTEL CORP·Filed 2014·Granted Jan 16, 2018·5 cites·20 claims
- 0366US9811341B2Managed instruction cache prefetchingSTAVROU KYRIAKOS A·Filed 2011·Granted Nov 7, 2017·4 cites·5 claims
- 0459US10013326B2Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code regionMARTINEZ RAUL·Filed 2011·Granted Jul 3, 2018·1 cites·18 claims
- 0552US2019004916A1Profiling asynchronous events resulting from the execution of software at code region granularityINTEL CORP·Filed 2018·Application pending·0 cites
- 0642US10157063B2Instruction and logic for optimization level aware branch predictionINTEL CORP·Filed 2012·Granted Dec 18, 2018·0 cites·6 claims
- 0737US2014156976A1Method, apparatus and system for selective execution of a commit instructionGIBERT CODINA ENRIC·Filed 2011·Application pending·0 cites
- 0832US2013326199A1Method and apparatus for controlling a mxcsrMAGKLIS GRIGORIOS·Filed 2011·Application pending·0 cites
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