US2019004916A1PendingUtilityA1

Profiling asynchronous events resulting from the execution of software at code region granularity

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Assignee: INTEL CORPPriority: Dec 29, 2011Filed: Jul 3, 2018Published: Jan 3, 2019
Est. expiryDec 29, 2031(~5.5 yrs left)· nominal 20-yr term from priority
G06F 11/3409G06F 11/3037G06F 12/0862G06F 2201/88G06F 2201/865G06F 2201/885G06F 2201/86G06F 11/3466
52
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Claims

Abstract

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Claims

exact text as granted — not AI-modified
1 . A processor comprising:
 (a) a first logic to indicate whether an instruction that has been fetched by the processor is within a code region for which profile information will be collected;   (b) a second logic to detect an asynchronous event related to the profile information being collected in response to performing the instruction that is within the code region and to produce a first signal in response thereto;   (c) a third logic to cause a record to be generated for each asynchronous event in response to the first signal, wherein the record comprises the profile information; and   (d) a fourth logic to store the profile information.   
     
     
         2 . The processor of  claim 1 , wherein the first logic is to compare an address for each instruction fetched to a low address and high address to determine if the address for the instruction is within a range bounded by the low address and high address, and if so, determines that the instruction is within the code region, but if not, determines that the software instruction is not with the code region. 
     
     
         3 . The processor of  claim 1 , wherein the first logic enables specific instructions to be specified as being at a beginning and at an end of the code region and then identifies each instruction that is between the specific software instructions specified as being within the code region. 
     
     
         4 . The processor of  claim 1 , wherein the first logic dynamically inserts special instructions at the beginning and at the end of the code region, and then identifies software instructions that are between the special instructions inserted as being within the code region. 
     
     
         5 . The processor of  claim 1 , wherein the first logic marks each asynchronous event related to the profile information being collected that is performed in response to an instruction within the code region, and wherein the second logic responds only to an event that is marked, while ignoring any event that is not marked. 
     
     
         6 . The processor of  claim 5 , wherein the first logic marks a prefetching memory request performed in response to instructions within the code region with a special prefetching profile bit that is propagated with the prefetching memory request when the prefetching memory request is issued, the second logic marking each line of a memory block requested by said prefetching memory request with the prefetching profile bit when placed in a memory cache, to indicate that the line was prefetched in response to a prefetch memory request instruction within the code region, the third logic responding to the marked lines to collect profile information related to asynchronous prefetching events, which is stored by the fourth logic. 
     
     
         7 . The processor of  claim 6 , wherein the fourth logic employs one or more event counters to store the profile information while instructions within the code region are being executed. 
     
     
         8 . The processor of  claim 7 , wherein the fourth logic resets the event counters and clears prefetching profile bits previously applied before collecting profile information related to asynchronous events performed in response to instructions within a new code region. 
     
     
         9 . The processor of  claim 1 , wherein the first logic indicates whether instructions fetched by the processor are within any of a plurality of different code regions for which profile information is being collected, the first logic then marking each such instruction with an identifier of the code region in which the instruction occurs, and wherein the second logic detects asynchronous events related to the profile information being collected in response to performing the instructions that are within the plurality of different code regions, to produce the first signal in response to each such event and marking results of executing the instructions in each of the plurality of code regions with the identifier of the code region in which the instructions occurred. 
     
     
         10 . The processor of  claim 9 , wherein one or more of the plurality of different code regions consists of a single instruction and the profile information for a code region consisting of a single instruction generated by the third logic is at an instruction level of granularity. 
     
     
         11 . The processor of  claim 1 , wherein the first logic designates a subset of instructions in the code region as instructions for which the profile information will be collected, and wherein the second logic marks results of executing the subset of instructions to indicate that the results were produced by executing the subset of instructions, the results including events of interest occurring due to execution of the subset of instructions. 
     
     
         12 . A machine implemented method to collect profile information in regard to instructions within a code region, comprising:
 (a) determining whether an instruction that has been fetched is within the code region;   (b) detecting each asynchronous event related to the profile information that is being collected, where said event occurs in response to performing an instruction determined to be within the code region;   (c) generating a record for each asynchronous event that is detected, wherein the record comprises the profile information; and   (d) storing the profile information.   
     
     
         13 . The method of  claim 12 , wherein each instruction being fetched is identified as being within the code region by:
 (a) setting a low address and a high address for the code region;   (b) comparing an address for each instruction being fetched to the low address and the high address to determine if the address for the instruction is within a range bounded by the low address and the high address; and, if so   (c) determining that the instruction is within the code region, but if not, determining that the software instruction is not within the code region.   
     
     
         14 . The method of  claim 12 , wherein each of the instruction being fetched is identified as being within the code region by:
 (a) specifying specific instructions as being at a beginning and at an end of the code region selected; and   (b) identifying each instruction that is between the specific instructions as being within the code region.   
     
     
         15 . The method of  claim 12 , wherein each of the instruction being fetched is identified as being within the code region by:
 (a) dynamically inserting special instructions at a beginning and at an end of the code region; and   (b) identifying each instruction between the special instructions as being within the code region.   
     
     
         16 . The method of  claim 12 , wherein each asynchronous event related to the profile information being collected for the code region is detected by:
 (a) marking an event related to the profile information being collected, if the event is triggered by execution of an instruction within the code region; and   (b) responding only to an event that is thus marked when generating the record of the event to be included in the profile information.   
     
     
         17 . The method of  claim 16 , wherein for collecting profile information relating to asynchronous prefetching events, each prefetching memory request generated by an instruction within the code region is marked with a special bit that is propagated with the prefetching memory request when the prefetching memory request is issued, each line of a memory block requested by said prefetching memory request being marked when placed in a memory cache, to indicate that the line was prefetched in response to a prefetch memory request instruction within the code region, the marked lines being used to collect the profile information relating to the asynchronous prefetching events. 
     
     
         18 . The method of  claim 12 , wherein the profile information is accumulated by one or more event counters to store the profile information while the instructions within the code region selected are being executed. 
     
     
         19 . The method of  claim 12 , further comprising determining whether instructions that have been fetched are within any of a plurality of different code regions for which profile information is being collected, marking each such instruction with an identifier of the code region in which the instruction occurs, simultaneously detecting asynchronous events related to the profile information that is being collected that are in response to performing the instruction determined to be within any of the plurality of different code regions, and marking results of executing the instructions in each of the plurality of code regions with the identifier of the code region in which the instruction occurred. 
     
     
         20 . The method of  claim 19 , wherein one or more of the plurality different code regions consists of a single instruction, and the profile information is collected for a code region consisting of a single instruction at an instruction level of granularity. 
     
     
         21 - 30 . (canceled)

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