Inventor · disambiguated record
Grigorios Magklis
Also filed as: MAGKLIS GRIGORIOS
39 granted patents·4 pending applications·388 citations·filing 2004–2019
97Inventor score
Top patents by PatentIndex Score
43 records- 0198US7434073B2Frequency and voltage scaling architectureINTEL CORP·Filed 2004·Granted Oct 7, 2008·219 cites·27 claims
- 0292US7930574B2Thread migration to improve power efficiency in a parallel processing environmentINTEL CORP·Filed 2007·Granted Apr 19, 2011·28 cites·18 claims
- 0391US9778909B2Double rounded combined floating-point multiply and addINTEL CORP·Filed 2016·Granted Oct 3, 2017·7 cites·11 claims
- 0487US7739537B2Multiple clock domain microprocessorALBONESI DAVID·Filed 2006·Granted Jun 15, 2010·23 cites·23 claims
- 0585US7814339B2Leakage power estimationINTEL CORP·Filed 2006·Granted Oct 12, 2010·15 cites·28 claims
- 0684US7089443B2Multiple clock domain microprocessorUNIV ROCHESTER·Filed 2004·Granted Aug 8, 2006·33 cites·12 claims
- 0783US9477441B2Double rounded combined floating-point multiply and addINTEL CORP·Filed 2015·Granted Oct 25, 2016·3 cites·10 claims
- 0883US8612698B2Replacement policy for hot code detectionLOPEZ PEDRO·Filed 2008·Granted Dec 17, 2013·16 cites·18 claims
- 0983US8166323B2Thread migration to improve power efficiency in a parallel processing environmentCAI QIONG·Filed 2011·Granted Apr 24, 2012·7 cites·17 claims
- 1078US11422808B2Transactional compare-and-discard instructionADVANCED RISC MACH LTD·Filed 2019·Granted Aug 23, 2022·2 cites·11 claims
- 1177US9213523B2Double rounded combined floating-point multiply and addSAMUDRALA SRIDHAR·Filed 2012·Granted Dec 15, 2015·5 cites·24 claims
- 1274US7665000B2Meeting point thread characterizationINTEL CORP·Filed 2007·Granted Feb 16, 2010·7 cites·15 claims
- 1372US11481290B2Exception handling in transactionsADVANCED RISC MACH LTD·Filed 2019·Granted Oct 25, 2022·1 cites·11 claims
- 1472US8806491B2Thread migration to improve power efficiency in a parallel processing environmentCAI QIONG·Filed 2012·Granted Aug 12, 2014·4 cites·20 claims
- 1570US9329848B2Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programsLUPON MARC·Filed 2013·Granted May 3, 2016·4 cites·20 claims
- 1668US9047014B2Frequency and voltage scaling architectureINTEL CORP·Filed 2014·Granted Jun 2, 2015·1 cites·20 claims
- 1766US9811341B2Managed instruction cache prefetchingSTAVROU KYRIAKOS A·Filed 2011·Granted Nov 7, 2017·4 cites·5 claims
- 1866US8190652B2Achieving coherence between dynamically optimized code and original codeLATORRE FERNANDO·Filed 2007·Granted May 29, 2012·4 cites·10 claims
- 1965US7698512B2Compressing address communications between processorsINTEL CORP·Filed 2007·Granted Apr 13, 2010·3 cites·28 claims
- 2059US10013326B2Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code regionMARTINEZ RAUL·Filed 2011·Granted Jul 3, 2018·1 cites·18 claims
- 2156US8407497B2Frequency and voltage scaling architectureMAGKLIS GRIGORIOS·Filed 2008·Granted Mar 26, 2013·1 cites·20 claims
- 2255US8689029B2Frequency and voltage scaling architectureINTEL CORP·Filed 2013·Granted Apr 1, 2014·0 cites·20 claims
- 2353US9374542B2Image signal processor with a block checking circuitINTEL CORP·Filed 2014·Granted Jun 21, 2016·0 cites·20 claims
- 2452US2019004916A1Profiling asynchronous events resulting from the execution of software at code region granularityINTEL CORP·Filed 2018·Application pending·0 cites
- 2551US10061587B2Instruction and logic for bulk register reclamationINTEL CORP·Filed 2014·Granted Aug 28, 2018·0 cites·20 claims
- 2650US11513796B2Multiply-accumulation in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted Nov 29, 2022·0 cites·19 claims
- 2748US11422807B2Testing bit values inside vector elementsADVANCED RISC MACH LTD·Filed 2018·Granted Aug 23, 2022·0 cites·17 claims
- 2848US11327752B2Element by vector operations in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted May 10, 2022·0 cites·23 claims
- 2948US9389871B2Combined floating point multiplier adder with intermediate rounding logicINTEL CORP·Filed 2013·Granted Jul 12, 2016·0 cites·30 claims
- 3047US11106465B2Vector add-with-carry instructionADVANCED RISC MACH LTD·Filed 2018·Granted Aug 31, 2021·0 cites·15 claims
- 3145US11663034B2Permitting unaborted processing of transaction after exception mask update instructionADVANCED RISC MACH LTD·Filed 2018·Granted May 30, 2023·0 cites·12 claims
- 3245US11579873B2Handling load-exclusive instructions in apparatus having support for transactional memoryADVANCED RISC MACH LTD·Filed 2019·Granted Feb 14, 2023·0 cites·11 claims
- 3344US11775297B2Transaction nesting depth testing instructionADVANCED RISC MACH LTD·Filed 2018·Granted Oct 3, 2023·0 cites·15 claims
- 3444US11615032B2Address translation data invalidationADVANCED RISC MACH LTD·Filed 2018·Granted Mar 28, 2023·0 cites·8 claims
- 3544US10824350B2Handling contingent and non-contingent memory access program instructions making use of disable flagADVANCED RISC MACH LTD·Filed 2017·Granted Nov 3, 2020·0 cites·15 claims
- 3643US11314514B2Vector length querying instructionADVANCED RISC MACH LTD·Filed 2016·Granted Apr 26, 2022·0 cites·13 claims
- 3742US11977884B2Replicate elements instructionADVANCED RISC MACH LTD·Filed 2017·Granted May 7, 2024·0 cites·16 claims
- 3842US11947962B2Replicate partition instructionADVANCED RISC MACH LTD·Filed 2017·Granted Apr 2, 2024·0 cites·16 claims
- 3942US10157063B2Instruction and logic for optimization level aware branch predictionINTEL CORP·Filed 2012·Granted Dec 18, 2018·0 cites·6 claims
- 4038US10430192B2Vector processing using loops of dynamic vector lengthADVANCED RISC MACH LTD·Filed 2016·Granted Oct 1, 2019·0 cites·12 claims
- 4138US2013268735A1Support for speculative ownership without dataGIBERT CODINA ENRIC·Filed 2011·Application pending·0 cites
- 4237US2014156976A1Method, apparatus and system for selective execution of a commit instructionGIBERT CODINA ENRIC·Filed 2011·Application pending·0 cites
- 4332US2013326199A1Method and apparatus for controlling a mxcsrMAGKLIS GRIGORIOS·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →