Inventor

DEWEY GILBERT

US386 patents

⚠️ This page may combine multiple inventors who share the name “DEWEY GILBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEWEY GILBERT

INTEL CORP

Method for making a semiconductor device having a high-k gate dielectric

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Forming high-k dielectric layers on smooth substrates

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Apparatus and methods for forming a modulation doped non-planar transistor

Method for making a semiconductor device having a high-k gate dielectric

Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions

Top-gate doped thin film transistor

Thin film transistors having U-shaped features

Backside contacts for semiconductor devices

Transistor structures with a metal oxide contact buffer

Vertical 1T-1C DRAM array

Group III-N nanowire transistors

Indium-rich NMOS transistor channels

High-mobility semiconductor source/drain spacer

Group III-N nanowire transistors

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Deep gate-all-around semiconductor device having germanium or group III-V active layer

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

Group III-N nanowire transistors

Lattice mismatched hetero-epitaxial film

Techniques for forming non-planar germanium quantum well devices

Techniques for forming non-planar germanium quantum well devices

Defect transferred and lattice mismatched epitaxial film

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

Trench confined epitaxially grown device layer(s)

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Non-planar germanium quantum well devices

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Techniques and configuration for stacking transistors of an integrated circuit device

Deep gate-all-around semiconductor device having germanium or group III-V active layer

DEWEY GILBERT

Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Non-planar semiconductor device having active region with multi-dielectric gate stack

Gate electrode having a capping layer

RADOSAVLJEVIC MARKO

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Conductivity improvements for III-V semiconductor devices

Non-planar semiconductor device having channel region with low band-gap cladding layer

THEN HAN WUI

Group III-N nanowire transistors

High voltage field effect transistors

Non-planar III-N transistor

MUKHERJEE NILOY

Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

DOYLE BRIAN S

Recessed channel array transistor (RCAT) structures

MAJHI PRASHANT

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs