High-mobility semiconductor source/drain spacer

Abstract

Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

What is claimed is: 
     
       1. A transistor, comprising:
 a fin comprising a first semiconductor material; 
 a gate stack over a lateral channel region of the first semiconductor material; and 
 a source and a drain comprising a second semiconductor material, the source and the drain each laterally spaced apart from the gate stack by a gate sidewall spacer, and each vertically spaced apart from the lateral channel region by a thickness of semiconductor material that has a lower impurity concentration than the second semiconductor material, wherein a first width of the fin beyond the gate sidewall spacer is greater than a second width of the fin within the lateral channel region. 
 
     
     
       2. The transistor of  claim 1 , wherein:
 the thickness of semiconductor material has substantially the same composition as the first semiconductor material; and 
 the first semiconductor material has a carrier mobility greater than that of silicon. 
 
     
     
       3. The transistor of  claim 2 , wherein:
 a first height of the fin from an underlying substrate at a location beyond the gate sidewall spacer is greater than a second height of the fin within the lateral channel region by an amount approximately equal to the thickness of the semiconductor material; and 
 the first width of the fin beyond the gate sidewall spacer is greater than a second width of the fin within the lateral channel region by an amount approximately equal to twice the thickness of the semiconductor material. 
 
     
     
       4. The transistor of  claim 1 , wherein:
 the first semiconductor material comprises is first III-V compound semiconductor material and the fin is over a sub-fin comprising a second III-V compound semiconductor; 
 the source and drain further comprise a third III-V compound semiconductor material in contact with the first III-V compound semiconductor material; and 
 the third III-V compound semiconductor is separated from the second III-V compound semiconductor material by the first III-V compound semiconductor material. 
 
     
     
       5. The transistor of  claim 1 , wherein:
 the fin is over a substrate comprising silicon; and 
 the first semiconductor material is an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb. 
 
     
     
       6. The transistor of  claim 5 , wherein:
 the first semiconductor material comprises a first III-V compound semiconductor material and the fin is on a sub-fin comprising a second III-V compound semiconductor is an alloy of AlSb, an alloy of GaSb, an alloy of GaAlSb, and alloy of GaAsSb, an alloy of InAlAs, an alloy of GaAs, or and alloy of AlGaAs. 
 
     
     
       7. The transistor of  claim 1 , wherein:
 the thickness of the semiconductor material vertically spacing the source/drain regions apart from the lateral channel region has the same impurity dopant concentration as the lateral channel region; 
 the gate sidewall spacer comprises a gate insulator of the gate stack; and 
 the gate sidewall spacer separates a sidewall of a metal gate electrode of the gate stack from a top surface of the semiconductor material vertically spacing the source and drain apart from the lateral channel region. 
 
     
     
       8. A CMOS integrated circuit (IC), comprising:
 a silicon substrate; 
 an n-type III-V-channeled fin field effect transistor (FET) over a first region of the substrate, the III-V finFET further including:
 a fin of a first III-V compound semiconductor material; 
 a metal-insulator gate stack and a gate stack sidewall spacer over a lateral channel region of the first III-V compound semiconductor material; and 
 a source and drain comprising a second semiconductor material, the source and drain each laterally spaced apart from the gate stack by a gate sidewall spacer, the source and drain vertically spaced apart from the lateral channel region by a thickness of semiconductor material having a lower impurity concentration than the second semiconductor material, wherein a first width of the fin beyond the gate sidewall spacer is greater than a second width of the fin within the lateral channel region; and 
 
 a p-type silicon-channeled finFET over a second region of the substrate. 
 
     
     
       9. The CMOS IC of  claim 8 , wherein:
 the thickness of the semiconductor material has substantially the same composition as the first semiconductor material; 
 the first semiconductor has a carrier mobility greater than that of silicon; 
 a first height of the fin from the substrate at a location beyond the gate sidewall spacer is greater than a second height of the fin within the lateral channel region by an amount approximately equal to the thickness of the semiconductor material; 
 the first width of the fin beyond the gate sidewall spacer is greater than the second width of the fin within the lateral channel region by an amount approximately equal to twice the thickness of the semiconductor material; and 
 the p-type finFET comprises a fin of a width equal to the second width. 
 
     
     
       10. The CMOS IC of  claim 8 , wherein:
 a gate length associated with the n-type finFET is less than a corresponding gate length associated with the p-type finFET; and 
 a difference between the effective channel length and the gate length of the n-type finFET is greater than that of an effective channel length of the p-type finFET. 
 
     
     
       11. The CMOS IC of  claim 10 , wherein a substrate area occupied by the n-type finFET is smaller than that occupied by the p-type finFET. 
     
     
       12. The CMOS IC of  claim 8 , wherein:
 the first semiconductor material comprises an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb. 
 
     
     
       13. A method of fabricating a high carrier mobility fin field effect transistor (FET), the method comprising:
 forming a fin over a substrate, the fin comprising a monocrystalline semiconductor material different than that of the substrate; 
 masking a lateral channel region of the fin having a first width; 
 epitaxially growing a spacer at ends of the fin beyond the masked lateral channel region, the spacer comprising a thickness of semiconductor material increasing the fin to a second width, greater than the first width; and 
 forming a source and a drain over the spacer at the ends of the fin, the source and the drain comprising an impurity dopant at a concentration that is higher than that within the spacer, and the source and drain vertically spaced apart from the lateral channel region by the thickness of semiconductor material. 
 
     
     
       14. The method of  claim 13 , further comprising forming a gate stack over the lateral channel region, and forming contact metallization to the source and drain. 
     
     
       15. The method of  claim 13 , wherein epitaxially growing the spacer further comprises growing, over the fin, an additional thickness of the semiconductor material present within the lateral channel region. 
     
     
       16. The method of  claim 13 , wherein epitaxially growing the spacer further comprises:
 recess etching the fin semiconductor material not covered by the mask; and 
 epitaxially growing a monocrystalline layer of the spacer semiconductor material along monocrystalline sidewall surfaces of the recessed fin semiconductor material. 
 
     
     
       17. The method of  claim 16 , wherein epitaxially growing the spacer semiconductor material further comprises growing a III-V compound semiconductor material having the same composition as the recessed fin semiconductor material. 
     
     
       18. The method of  claim 16 , wherein:
 recess etching the fin semiconductor material exposes a surface of a sub-fin located below the fin, the sub-fin further comprising a second semiconductor material; and 
 epitaxially growing the layer of the spacer semiconductor material further comprises growing the spacer semiconductor material on the exposed surface of the second semiconductor material, and on a sidewall surface of the fin semiconductor material. 
 
     
     
       19. The method of  claim 13 , wherein forming the mask over the lateral channel region further comprises:
 depositing a sacrificial gate stack; 
 patterning the sacrificial gate stack into a stripe extending over the lateral channel region; and 
 forming a lateral spacer adjacent to sidewalls of the stripe, the lateral spacer comprising a dielectric material. 
 
     
     
       20. The method of  claim 14 , wherein forming the gate stack over the lateral channel region further comprises:
 recess etching the fin semiconductor within the lateral channel region after removing the mask; 
 depositing a high-k gate dielectric material over recessed fin semiconductor within the lateral channel region; and 
 depositing a gate metal over the high-k gate dielectric. 
 
     
     
       21. The method of  claim 13 , wherein:
 forming the fin further comprises forming a fin comprising an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb.