Inventor · disambiguated record
Tahir Ghani
Also filed as: GHANI TAHIR
504 granted patents·264 pending applications·3,972 citations·filing 1996–2025
99Inventor score
Top patents by PatentIndex Score
768 records- 0199US11251281B2Contact resistance reduction employing germanium overlayer pre-contact metalizationINTEL CORP·Filed 2020·Granted Feb 15, 2022·5 cites·20 claims
- 0299US6885084B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Apr 26, 2005·159 cites·12 claims
- 0399US6861318B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Mar 1, 2005·165 cites·11 claims
- 0499US6621131B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2001·Granted Sep 16, 2003·534 cites·20 claims
- 0598US11923410B2Transistor with isolation below source and drainINTEL CORP·Filed 2021·Granted Mar 5, 2024·4 cites·23 claims
- 0698US11887891B2Self-aligned contactsINTEL CORP·Filed 2023·Granted Jan 30, 2024·2 cites·20 claims
- 0798US11855223B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devicesINTEL CORP·Filed 2021·Granted Dec 26, 2023·6 cites·20 claims
- 0898US11616015B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2020·Granted Mar 28, 2023·3 cites·19 claims
- 0998US11087832B1Three-dimensional nanoribbon-based static random-access memoryINTEL CORP·Filed 2020·Granted Aug 10, 2021·18 cites·20 claims
- 1098US10304940B1Gate cut and fin trim isolation for advanced integrated circuit structure fabricationINTEL CORP·Filed 2017·Granted May 28, 2019·13 cites·20 claims
- 1198US9583491B2CMOS nanowire structureKIM SEIYON·Filed 2015·Granted Feb 28, 2017·28 cites·15 claims
- 1298US9349810B2Selective germanium P-contact metalization through trenchINTEL CORP·Filed 2015·Granted May 24, 2016·17 cites·20 claims
- 1398US9224810B2CMOS nanowire structureKIM SEIYON·Filed 2011·Granted Dec 29, 2015·44 cites·23 claims
- 1498US9117791B2Selective germanium P-contact metalization through trenchGLASS GLENN A·Filed 2011·Granted Aug 25, 2015·38 cites·22 claims
- 1598US8847281B2High mobility strained channels for fin-based transistorsCEA STEPHEN M·Filed 2012·Granted Sep 30, 2014·47 cites·22 claims
- 1698US8436404B2Self-aligned contactsBOHR MARK T·Filed 2009·Granted May 7, 2013·148 cites·30 claims
- 1798US7402872B2Method for forming an integrated circuitINTEL CORP·Filed 2006·Granted Jul 22, 2008·141 cites·15 claims
- 1898US6521964B1Device having spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Feb 18, 2003·241 cites·6 claims
- 1998US6509618B2Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Jan 21, 2003·239 cites·8 claims
- 2098US6506652B2Method of recessing spacers to improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jan 14, 2003·239 cites·9 claims
- 2197US11031487B2Contact over active gate structures for advanced integrated circuit structure fabricationINTEL CORP·Filed 2019·Granted Jun 8, 2021·7 cites·20 claims
- 2297US10886217B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2016·Granted Jan 5, 2021·20 cites·20 claims
- 2397US10615265B2Gate cut and fin trim isolation for advanced integrated circuit structure fabricationINTEL CORP·Filed 2019·Granted Apr 7, 2020·8 cites·5 claims
- 2497US9882027B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2014·Granted Jan 30, 2018·12 cites·8 claims
- 2597US9859368B2Integration methods to fabricate internal spacers for nanowire devicesINTEL CORP·Filed 2016·Granted Jan 2, 2018·11 cites·15 claims
- 2697US9728464B2Self-aligned 3-D epitaxial structures for MOS device fabricationGLASS GLENN A·Filed 2012·Granted Aug 8, 2017·28 cites·30 claims
- 2797US9716037B2Gate aligned contact and method to fabricate sameGOLONZKA OLEG·Filed 2011·Granted Jul 25, 2017·65 cites·15 claims
- 2897US9508821B2Self-aligned contactsINTEL CORP·Filed 2015·Granted Nov 29, 2016·13 cites·3 claims
- 2997US9484447B2Integration methods to fabricate internal spacers for nanowire devicesKIM SEIYON·Filed 2012·Granted Nov 1, 2016·35 cites·9 claims
- 3097US9484432B2Contact resistance reduction employing germanium overlayer pre-contact metalizationINTEL CORP·Filed 2015·Granted Nov 1, 2016·14 cites·20 claims
- 3197US9466565B2Self-aligned contactsINTEL CORP·Filed 2015·Granted Oct 11, 2016·24 cites·18 claims
- 3297US9153583B2III-V layers for N-type and P-type MOS source-drain contactsGLASS GLENN A·Filed 2011·Granted Oct 6, 2015·28 cites·25 claims
- 3397US9054178B2Self-aligned contactsBOHR MARK T·Filed 2014·Granted Jun 9, 2015·30 cites·12 claims
- 3497US9041146B2Logic chip including embedded magnetic tunnel junctionsINTEL CORP·Filed 2013·Granted May 26, 2015·30 cites·24 claims
- 3597US8994104B2Contact resistance reduction employing germanium overlayer pre-contact metalizationGLASS GLENN A·Filed 2011·Granted Mar 31, 2015·41 cites·23 claims
- 3697US8901537B2Transistors with high concentration of boron doped germaniumMURTHY ANAND S·Filed 2010·Granted Dec 2, 2014·56 cites·25 claims
- 3797US8313999B2Multi-gate semiconductor device with self-aligned epitaxial source and drainCAPPELLANI ANNALISA·Filed 2009·Granted Nov 20, 2012·70 cites·14 claims
- 3896US12342612B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2023·Granted Jun 24, 2025·2 cites·20 claims
- 3996US12266708B2Integrated circuit structures having dielectric anchor voidINTEL CORP·Filed 2023·Granted Apr 1, 2025·2 cites·25 claims
- 4096US12021149B2Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2023·Granted Jun 25, 2024·2 cites·20 claims
- 4196US11862635B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2022·Granted Jan 2, 2024·2 cites·20 claims
- 4296US11843058B2Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structuresINTEL CORP·Filed 2021·Granted Dec 12, 2023·3 cites·18 claims
- 4396US11824107B2Wrap-around contact structures for semiconductor nanowires and nanoribbonsINTEL CORP·Filed 2022·Granted Nov 21, 2023·2 cites·20 claims
- 4496US11799037B2Gate-all-around integrated circuit structures having asymmetric source and drain contact structuresINTEL CORP·Filed 2022·Granted Oct 24, 2023·2 cites·23 claims
- 4596US11640988B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2021·Granted May 2, 2023·2 cites·23 claims
- 4696US11018264B1Three-dimensional nanoribbon-based logicINTEL CORP·Filed 2019·Granted May 25, 2021·18 cites·20 claims
- 4796US10541316B2Contact over active gate structures for advanced integrated circuit structure fabricationINTEL CORP·Filed 2017·Granted Jan 21, 2020·9 cites·25 claims
- 4896US10304946B2Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devicesINTEL CORP·Filed 2015·Granted May 28, 2019·11 cites·21 claims
- 4996US9831306B2Self-aligned gate edge and local interconnect and method to fabricate sameINTEL CORP·Filed 2013·Granted Nov 28, 2017·29 cites·45 claims
- 5096US9722023B2Selective germanium P-contact metalization through trenchINTEL CORP·Filed 2016·Granted Aug 1, 2017·9 cites·20 claims
Showing the top 50 of 768 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →