Inventor

PHELPS RICHARD A

US54 patents

⚠️ This page may combine multiple inventors who share the name “PHELPS RICHARD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PHELPS RICHARD A

IBM

Asymmetric junction field effect transistor

Wrapped gate junction field effect transistor

Junction field effect transistor with a hyperabrupt junction

Structure and method for fabrication JFET in CMOS

Pixel sensor cell having reduced pinning layer barrier potential and method thereof

Method for applying a layer to a hydrophobic surface

High voltage laterally diffused metal oxide semiconductor

Back-end-of-line metal-oxide-semiconductor varactors

Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

Method of forming pixel sensor cell having reduced pinning layer barrier potential

Compensation for a charge in a silicon substrate

Method for detection of photolithographic defocus

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

Silicon controlled rectifier with stress-enhanced adjustable trigger voltage

Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode

Asymmetric wedge JFET, related method and design structure

Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

Double gate depletion mode MOSFET

Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit

High resistivity substrate final resistance test structure

CHIVAS PRODUCTS

Dual action cupholder

Nested container holders

Bilateral beverage container holder

Vehicle door pocket

Visor mount

Container holder

Padded automotive casket handle

Method and apparatus for producing trim panels

Assist strap termination structure

Cold sealing process for soft trim products

BOTULA ALAN B

Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate

Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method

Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

Silicon-on-insulator substrate and method of forming

GLOBALFOUNDRIES INC

Multiple back gate transistor

Air gaps formed by porous silicon removal

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

ANDERSON FREDERICK G

Isolated Zener diode

Asymmetric junction field effect transistor

CAMILLO-CASTILLO RENATA

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

Silicon controlled rectifier with stress-enhanced adjustable trigger voltage

LIU XUEFENG

Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

Asymmetric wedge JFET, related method and design structure

GRECO JOSEPH R

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region

BECKER GROUP INC

Method and apparatus for producing trim panels

CAMPI JOHN B

Double gate depletion mode MOSFET

HERSHBERGER DOUGLAS B

Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET

DEMUYNCK DAVID A

Apparatus for applying a layer to a hydrophobic surface

CAMILLO-CASTILLO RENATA A

Structure and method to create stress trench