Dual shallow trench isolation (STI) structure for field effect transistor (FET)

Abstract

Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

We claim: 
     
       1. A structure for a filed effect transistor (FET) comprising:
 a deep n-type well in a substrate; 
 a shallow n-type well within the deep n-type well; and 
 a shallow trench isolation (STI) region at least partially within the shallow n-type well, the STI region including: 
 a plurality of first sections within the deep n-type well, each of the plurality of first sections being laterally separated from an adjacent first section by a respective portion of the deep n-type well, and 
 a second section within the shallow n-type well and contacting each of the plurality of first sections, wherein the second section overlies and extends laterally beyond each of the plurality of first sections, wherein the second section includes a lower surface contacting and overlying the deep n-type well, and 
 a gate region disposed directly over portions of all the plurality of the first sections. 
 
     
     
       2. The structure of  claim 1 , wherein the second section of the STI region includes silicon oxide. 
     
     
       3. The structure of  claim 1 , wherein a lateral width of the second section is greater than a combined lateral width of the plurality of first sections. 
     
     
       4. The structure of  claim 1 , wherein the second section of the STI region includes a portion contacting and overlying the shallow n-type well. 
     
     
       5. The structure of  claim 1 , wherein the second section of the STI region includes a portion extending laterally beyond each of the first sections within the shallow n-type well. 
     
     
       6. The structure of  claim 1 , further comprising:
 the gate region overlying and contacting the second section of the STI region. 
 
     
     
       7. The structure of  claim 6 , further comprising:
 a p-type well within the deep n-type well, wherein the gate region contacts and overlies the shallow n-type well and the p-type well. 
 
     
     
       8. A structure for a field effect transistor (FET), comprising:
 a deep n-type well in a substrate; 
 a shallow n-type well within the deep n-type well, and 
 a multi-layer shallow trench isolation (STI) region within the shallow n-type well and deep n-type well, the multi-layer STI region including: 
 a plurality of first sections positioned within the deep n-type well, wherein a lower surface of each of the plurality of the first sections is buried within the deep n-type well, each of the plurality of the first sections being laterally separated from an adjacent first section by a respective portion of the deep n-type well, and 
 a blanket layer second section contacting and overlaying the plurality of the first sections, wherein an upper surface of the blanket layer second section is substantially coplanar with an upper surface of the shallow n-type well, and wherein a lower surface of the blanket layer second section is substantially coplanar with an upper surface of the deep n-type well. 
 
     
     
       9. The FET structure of  claim 8 , wherein the first section includes silicon oxide.