Inventor · disambiguated record
Richard A. Phelps
Also filed as: PHELPS RICHARD · PHELPS RICHARD A
55 granted patents·5 pending applications·681 citations·filing 1986–2018
98Inventor score
Top patents by PatentIndex Score
60 records- 0193US9761525B1Multiple back gate transistorGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·10 cites·19 claims
- 0293US5060899ANested container holdersCHIVAS PRODUCTS·Filed 1990·Granted Oct 29, 1991·136 cites·20 claims
- 0391US8492866B1Isolated Zener diodeANDERSON FREDERICK G·Filed 2012·Granted Jul 23, 2013·15 cites·23 claims
- 0490US9755015B1Air gaps formed by porous silicon removalGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 5, 2017·6 cites·11 claims
- 0590US7943445B2Asymmetric junction field effect transistorIBM·Filed 2009·Granted May 17, 2011·16 cites·10 claims
- 0690US4928865ABilateral beverage container holderCHIVAS PRODUCTS·Filed 1989·Granted May 29, 1990·83 cites·19 claims
- 0789US7825441B2Junction field effect transistor with a hyperabrupt junctionIBM·Filed 2007·Granted Nov 2, 2010·16 cites·35 claims
- 0888US8299537B2Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing regionGRECO JOSEPH R·Filed 2009·Granted Oct 30, 2012·22 cites·10 claims
- 0986US8168500B2Double gate depletion mode MOSFETCAMPI JOHN B·Filed 2011·Granted May 1, 2012·8 cites·20 claims
- 1086US7670889B2Structure and method for fabrication JFET in CMOSIBM·Filed 2008·Granted Mar 2, 2010·12 cites·19 claims
- 1185US8598660B2Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltageCAMILLO-CASTILLO RENATA·Filed 2011·Granted Dec 3, 2013·7 cites·11 claims
- 1284US7205591B2Pixel sensor cell having reduced pinning layer barrier potential and method thereofIBM·Filed 2005·Granted Apr 17, 2007·6 cites·16 claims
- 1384US4955571ADual action cupholderCHIVAS PRODUCTS·Filed 1989·Granted Sep 11, 1990·60 cites·16 claims
- 1482US8169007B2Asymmetric junction field effect transistorANDERSON FREDERICK G·Filed 2011·Granted May 1, 2012·6 cites·15 claims
- 1580US7459360B2Method of forming pixel sensor cell having reduced pinning layer barrier potentialIBM·Filed 2007·Granted Dec 2, 2008·4 cites·11 claims
- 1679US8748285B2Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrateBOTULA ALAN B·Filed 2011·Granted Jun 10, 2014·5 cites·12 claims
- 1778US8466501B2Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFETHERSHBERGER DOUGLAS B·Filed 2010·Granted Jun 18, 2013·8 cites·19 claims
- 1878US7977714B2Wrapped gate junction field effect transistorIBM·Filed 2007·Granted Jul 12, 2011·7 cites·14 claims
- 1976US7384878B2Method for applying a layer to a hydrophobic surfaceIBM·Filed 2005·Granted Jun 10, 2008·6 cites·32 claims
- 2075US5261716AVehicle door pocketCHIVAS PRODUCTS·Filed 1992·Granted Nov 16, 1993·39 cites·24 claims
- 2175US4686741APadded automotive casket handleCHIVAS PRODUCTS·Filed 1986·Granted Aug 18, 1987·38 cites·5 claims
- 2274US8698244B2Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and methodBOTULA ALAN B·Filed 2009·Granted Apr 15, 2014·4 cites·20 claims
- 2374US8586423B2Silicon controlled rectifier with stress-enhanced adjustable trigger voltageCAMILLO-CASTILLO RENATA·Filed 2011·Granted Nov 19, 2013·3 cites·16 claims
- 2474US8471340B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureBOTULA ALAN B·Filed 2009·Granted Jun 25, 2013·4 cites·25 claims
- 2573US9059276B2High voltage laterally diffused metal oxide semiconductorIBM·Filed 2013·Granted Jun 16, 2015·3 cites·19 claims
- 2673US4907775AContainer holderCHIVAS PRODUCTS·Filed 1989·Granted Mar 13, 1990·41 cites·18 claims
- 2772US8809155B2Back-end-of-line metal-oxide-semiconductor varactorsIBM·Filed 2012·Granted Aug 19, 2014·3 cites·9 claims
- 2871US8828746B2Compensation for a charge in a silicon substrateIBM·Filed 2012·Granted Sep 9, 2014·2 cites·18 claims
- 2971US5062608AVisor mountCHIVAS PRODUCTS·Filed 1990·Granted Nov 5, 1991·38 cites·22 claims
- 3068US8536035B2Silicon-on-insulator substrate and method of formingBOTULA ALAN B·Filed 2012·Granted Sep 17, 2013·2 cites·19 claims
- 3167US9383404B2High resistivity substrate final resistance test structureIBM·Filed 2014·Granted Jul 5, 2016·1 cites·20 claims
- 3267US8754455B2Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structureLIU XUEFENG·Filed 2011·Granted Jun 17, 2014·2 cites·19 claims
- 3365US8709903B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureIBM·Filed 2013·Granted Apr 29, 2014·1 cites·14 claims
- 3464US8946799B2Silicon controlled rectifier with stress-enhanced adjustable trigger voltageIBM·Filed 2013·Granted Feb 3, 2015·1 cites·18 claims
- 3563US9034712B2Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltageIBM·Filed 2013·Granted May 19, 2015·1 cites·11 claims
- 3663US5562797AMethod and apparatus for producing trim panelsBECKER GROUP INC·Filed 1994·Granted Oct 8, 1996·18 cites·8 claims
- 3757US8181593B2Apparatus for applying a layer to a hydrophobic surfaceDEMUYNCK DAVID A·Filed 2008·Granted May 22, 2012·2 cites·14 claims
- 3857US5326417AMethod and apparatus for producing trim panelsCHIVAS PRODUCTS·Filed 1993·Granted Jul 5, 1994·16 cites·22 claims
- 3955US8564067B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureIBM·Filed 2013·Granted Oct 22, 2013·0 cites·8 claims
- 4054US8618583B2Junction gate field effect transistor structure having n-channelCANDRA PANGLIJEN·Filed 2011·Granted Dec 31, 2013·1 cites·20 claims
- 4154US8227318B2Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formationLEVY MAX·Filed 2009·Granted Jul 24, 2012·1 cites·10 claims
- 4254US7902606B2Double gate depletion mode MOSFETIBM·Filed 2008·Granted Mar 8, 2011·0 cites·12 claims
- 4354US6968288B2Method for detection of photolithographic defocusIBM·Filed 2003·Granted Nov 22, 2005·5 cites·30 claims
- 4453US8921172B2Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structureIBM·Filed 2014·Granted Dec 30, 2014·0 cites·20 claims
- 4553US8779476B2Asymmetric wedge JFET, related method and design structureIBM·Filed 2013·Granted Jul 15, 2014·0 cites·17 claims
- 4653US2014306325A1Compensation for a charge in a silicon substrateIBM·Filed 2014·Application pending·0 cites
- 4751US8796108B2Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diodeIBM·Filed 2013·Granted Aug 5, 2014·0 cites·19 claims
- 4851US8242584B2Structure and method to create stress trenchCAMILLO-CASTILLO RENATA A·Filed 2009·Granted Aug 14, 2012·0 cites·16 claims
- 4951US2018204926A1Transistor using selective undercut at gate conductor and gate insulator cornerGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 5050US2014327084A1Dual shallow trench isolation (sti) field effect transistor (fet) and methods of formingIBM·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →