Dual shallow trench isolation (sti) field effect transistor (fet) and methods of forming

Abstract

Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

We claim: 
     
         1 . A field effect transistor (FET) structure, comprising:
 a deep n-type well;   a shallow n-type well and a p-type well each within the deep n-type well; and   a shallow trench isolation (STI) region within the shallow n-type well, the STI region including:
 a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and 
 a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well. 
   
     
     
         2 . The FET structure of  claim 1 , wherein the second section includes a zero-level mask material. 
     
     
         3 . The FET structure of  claim 2 , wherein the second section has a greater width than the first section. 
     
     
         4 . The FET structure of  claim 2 , wherein the second section includes a portion extending above the shallow n-type well. 
     
     
         5 . The FET structure of  claim 1 , wherein the second section extends laterally beyond the first section within the shallow n-type well. 
     
     
         6 . The FET structure of  claim 5 , wherein a portion of the first section includes an upper surface that is coplanar with an upper surface of the second section. 
     
     
         7 . The FET structure of  claim 1 , further comprising a contact layer overlying the STI region and extending from the p-type well to the shallow n-type well. 
     
     
         8 . The FET structure of  claim 1 , further comprising a substrate, wherein the deep n-type well overlies the substrate. 
     
     
         9 . The FET structure of  claim 1 , wherein the FET structure includes a high-voltage complementary metal oxide semiconductor (HVCMOS) FET structure. 
     
     
         10 . The FET structure of  claim 1 , wherein the second section includes a substantially rounded profile proximate at least one lateral edge thereof. 
     
     
         11 . A method comprising:
 forming a shallow n-type well within a deep n-type well; and   forming a dual-level shallow trench isolation (STI) within the shallow n-type well, the dual-level STI including:
 a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and 
 a second section contacting and overlying the first section, the second section having a second depth within the p-type well as measured from the upper surface of the shallow n-type well. 
   
     
     
         12 . The method of  claim 11 , wherein the forming of the dual-level STI within the shallow n-type well region includes:
 etching the shallow n-type well within the deep n-type well to form a first trench having a first width;   forming a pad oxide over the shallow n-type well including the first trench; and   forming a pad nitride over the pad oxide.   
     
     
         13 . The method of  claim 12 , wherein the forming of the dual-level STI further includes:
 forming a mask over the pad nitride; and   etching the pad nitride, the pad oxide, and the shallow n-type well within the deep n-type well layer to form a second trench above the first trench, the second trench having a second width distinct from the first width.   
     
     
         14 . The method of  claim 12 , wherein the forming of the pad oxide includes forming the pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the shallow n-type well. 
     
     
         15 . The method of  claim 14 , wherein the forming of the pad nitride includes forming the pad oxide to substantially cover the pad oxide. 
     
     
         16 . A method comprising:
 forming a first trench in a doped substrate;   forming a pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the doped substrate;   forming a pad nitride over the pad oxide;   forming a mask over the pad nitride to define a shallow trench isolation (STI) window; and   etching the pad nitride, the pad oxide and the doped substrate to form a second trench below the first trench and connected with the first trench, the second trench having a distinct width from a width of the first trench.   
     
     
         17 . The method of  claim 16 , wherein the forming of the pad nitride includes depositing the pad nitride to cover the pad oxide over the bottom of the first trench, sidewalls of the first trench and the upper surface of the doped substrate. 
     
     
         18 . The method of  claim 16 , wherein the forming of the mask over the pad nitride includes depositing the mask over the pad nitride and exposing the mask to define the STI window. 
     
     
         19 . The method of  claim 16 , wherein the first trench and the second trench collectively form a stepped surface. 
     
     
         20 . The method of  claim 16 , wherein the STI window has a width substantially equal to the width of the second trench.