Inventor · disambiguated record
Max G. Levy
Also filed as: LEVY MAX · LEVY MAX G · LEVY MAX GERALD
41 granted patents·3 pending applications·628 citations·filing 1996–2018
98Inventor score
Top patents by PatentIndex Score
44 records- 0194US6483172B1Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface statesSIEMENS AG·Filed 2000·Granted Nov 19, 2002·90 cites·11 claims
- 0293US7883990B2High resistivity SOI base wafer using thermally annealed substrateIBM·Filed 2007·Granted Feb 8, 2011·29 cites·7 claims
- 0390US10050115B2Tapered gate oxide in LDMOS devicesIBM·Filed 2014·Granted Aug 14, 2018·11 cites·10 claims
- 0487US7239376B2Method and apparatus for correcting gravitational sag in photomasks used in the production of electronic devicesIBM·Filed 2005·Granted Jul 3, 2007·10 cites·7 claims
- 0586US6388305B1Electrically programmable antifuses and methods for forming the sameIBM·Filed 1999·Granted May 14, 2002·78 cites·22 claims
- 0683US9893157B1Structures with contact trenches and isolation trenchesGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 13, 2018·4 cites·20 claims
- 0783US9337310B2Low leakage, high frequency devicesIBM·Filed 2014·Granted May 10, 2016·5 cites·18 claims
- 0883US6633055B2Electronic fuse structure and method of manufacturingIBM·Filed 1999·Granted Oct 14, 2003·69 cites·8 claims
- 0982US10224225B2Centering substrates on a chuckIBM·Filed 2018·Granted Mar 5, 2019·2 cites·20 claims
- 1082US7485965B2Through via in ultra high resistivity wafer and related methodsIBM·Filed 2007·Granted Feb 3, 2009·10 cites·9 claims
- 1180US9997385B2Centering substrates on a chuckIBM·Filed 2017·Granted Jun 12, 2018·2 cites·19 claims
- 1280US6103592AManufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesasIBM·Filed 1997·Granted Aug 15, 2000·68 cites·16 claims
- 1379US9685362B2Apparatus and method for centering substrates on a chuckIBM·Filed 2014·Granted Jun 20, 2017·3 cites·24 claims
- 1479US5721448AIntegrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst materialIBM·Filed 1996·Granted Feb 24, 1998·45 cites·7 claims
- 1578US5824580AMethod of manufacturing an insulated gate field effect transistorIBM·Filed 1996·Granted Oct 20, 1998·56 cites·9 claims
- 1676US9548349B2Semiconductor device with metal extrusion formationIBM·Filed 2014·Granted Jan 17, 2017·2 cites·11 claims
- 1776US9508578B2Method and apparatus for detecting foreign material on a chuckGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 29, 2016·3 cites·18 claims
- 1875US8487379B2Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applicationsLEVY MAX G·Filed 2012·Granted Jul 16, 2013·3 cites·19 claims
- 1974US8698244B2Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and methodBOTULA ALAN B·Filed 2009·Granted Apr 15, 2014·4 cites·20 claims
- 2074US8471340B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureBOTULA ALAN B·Filed 2009·Granted Jun 25, 2013·4 cites·25 claims
- 2171US6812122B2Method for forming a voltage programming elementIBM·Filed 2002·Granted Nov 2, 2004·16 cites·7 claims
- 2268US7772083B2Trench forming method and structureIBM·Filed 2008·Granted Aug 10, 2010·4 cites·20 claims
- 2365US8709903B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureIBM·Filed 2013·Granted Apr 29, 2014·1 cites·14 claims
- 2463US8188570B2Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applicationsLEVY MAX G·Filed 2010·Granted May 29, 2012·1 cites·20 claims
- 2561US7675121B2SOI substrate contact with extended silicide areaIBM·Filed 2007·Granted Mar 9, 2010·2 cites·16 claims
- 2660US6361402B1Method for planarizing photoresistIBM·Filed 1999·Granted Mar 26, 2002·26 cites·22 claims
- 2760US5804490AMethod of filling shallow trenchesIBM·Filed 1997·Granted Sep 8, 1998·27 cites·6 claims
- 2857US9825119B2Semiconductor device with metal extrusion formationIBM·Filed 2016·Granted Nov 21, 2017·0 cites·11 claims
- 2957US9825120B2Semiconductor device with metal extrusion formationIBM·Filed 2016·Granted Nov 21, 2017·0 cites·8 claims
- 3056US7939896B2SOI substrate contact with extended silicide areaIBM·Filed 2009·Granted May 10, 2011·1 cites·10 claims
- 3155US8564067B2Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structureIBM·Filed 2013·Granted Oct 22, 2013·0 cites·8 claims
- 3254US8227318B2Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formationLEVY MAX·Filed 2009·Granted Jul 24, 2012·1 cites·10 claims
- 3354US7842580B2Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applicationsIBM·Filed 2008·Granted Nov 30, 2010·0 cites·17 claims
- 3452US9059258B2Controlled metal extrusion opening in semiconductor structure and method of formingIBM·Filed 2013·Granted Jun 16, 2015·0 cites·14 claims
- 3551US9484301B2Controlled metal extrusion opening in semiconductor structure and method of formingGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 1, 2016·0 cites·2 claims
- 3650US2014327084A1Dual shallow trench isolation (sti) field effect transistor (fet) and methods of formingIBM·Filed 2013·Application pending·0 cites
- 3749US9595579B2Dual shallow trench isolation (STI) structure for field effect transistor (FET)GLOBALFOUNDRIES INC·Filed 2015·Granted Mar 14, 2017·0 cites·9 claims
- 3848US6372573B2Self-aligned trench capacitor capping process for high density DRAM cellsTOSHIBA KK·Filed 1999·Granted Apr 16, 2002·10 cites·14 claims
- 3948US6121106AMethod for forming an integrated trench capacitorIBM·Filed 1998·Granted Sep 19, 2000·10 cites·7 claims
- 4047US6518145B1Methods to control the threshold voltage of a deep trench corner deviceIBM·Filed 1998·Granted Feb 11, 2003·10 cites·10 claims
- 4144US5976982AMethods for protecting device components from chemical mechanical polish induced defectsSIEMENS AG·Filed 1997·Granted Nov 2, 1999·12 cites·19 claims
- 4240US5757059AInsulated gate field effect transistorIBM·Filed 1996·Granted May 26, 1998·9 cites·7 claims
- 4338US2009093092A1Soi substrate contact with extended silicide areaDANG DINH·Filed 2007·Application pending·0 cites
- 4430US2001014513A1Sti divot and seam eliminationFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →