Transistor using selective undercut at gate conductor and gate insulator corner

Abstract

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

What is claimed is: 
     
         1 . A method comprising:
 doping a substrate to have an active region bordered by an isolation region;   doping the active region to have a channel area;   growing a gate insulator on and contacting the channel area;   patterning a gate conductor on and contacting the gate insulator, the gate insulator is between the gate conductor and the channel area, the gate conductor is patterned to extend from the active region to the isolation region, the gate conductor is patterned to have a first section, a second section, a third section, and a fourth section, the fourth section is perpendicular to the first section, the second section of the gate conductor is between the first section and the third section of the gate conductor, the first section of the gate conductor is within the active region and has a first width, the third section of the gate conductor is within the isolation region and has a second width that is greater than the first width, and the second section of the gate conductor is within the active region and has a tapered width that tapers from the first width to the second width;   forming undercut regions in the first section, the second section, and the fourth section of the gate conductor where a corner of the gate conductor contacts the gate insulator, the third section of the gate conductor lacks the undercut regions;   forming additional amounts of the gate insulator in the undercut regions, the gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region; and   doping the active region to have a source area and a drain area, the channel area is between the source area and the drain area.   
     
     
         2 . The method according to  claim 1 , the fourth section comprises a second gate conductor. 
     
     
         3 . The method according to  claim 2 , the second gate conductor is patterned to connect to gate conductors of adjacent structures. 
     
     
         4 . The method according to  claim 1 , the gate conductor has sides, one of the sides is oriented toward the source area and another of the sides is oriented toward the drain area, and the undercut regions are only on one of the sides of the gate conductor. 
     
     
         5 . The method according to  claim 1 , further comprising forming electrical contacts to the third section of the gate conductor. 
     
     
         6 . The method according to  claim 1 , a size of the undercut regions, and a difference in thickness of the gate insulator in the undercut regions relative to where the corner of the gate conductor lacks the undercut regions in the isolation region, control overlap capacitance, breakdown voltage, and gate-induced drain leakage current. 
     
     
         7 . A method comprising:
 doping a substrate to have an active region bordered by an isolation region;   doping the active region to have a channel area;   growing a gate insulator on and contacting the channel area;   patterning a first gate conductor on and contacting the gate insulator, the gate insulator is between the first gate conductor and the channel area, the first gate conductor is patterned to extend from the active region to the isolation region, the first gate conductor is patterned to have a first section, a second section, and a third section, the second section of the first gate conductor is between the first section and the third section of the first gate conductor, the first section of the first gate conductor is within the active region and has a first width, the third section of the first gate conductor is within the isolation region and has a second width that is greater than the first width, and the second section of the first gate conductor is within the active region and has a tapered width that tapers from the first width to the second width;   patterning a second gate conductor perpendicular to the first gate conductor, the gate insulator is between the substrate and the second gate conductor, the second gate conductor has a fourth section within the active region, and the fourth section of the second gate conductor faces the first section of the first gate conductor;   forming undercut regions in the first section and the second section of the first gate conductor where a corner of the first gate conductor contacts the gate insulator, and in the fourth section of the second gate conductor where the second gate conductor contacts the second gate insulator, wherein the third section of the first gate conductor lacks the undercut regions;   forming additional amounts of the gate insulator in the undercut regions, the gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the first gate conductor lacks the undercut regions in the isolation region; and   doping the active region to have a source area and a drain area, the channel area is between the source area and the drain area.   
     
     
         8 . The method according to  claim 7 , the first gate conductor and the second gate conductor are formed in the same process. 
     
     
         9 . The method according to  claim 7 , the second gate conductor is patterned to connect to gate conductors of adjacent structures. 
     
     
         10 . The method according to  claim 7 , the undercut regions are only on one side of the first gate conductor. 
     
     
         11 . The method according to  claim 7 , further comprising forming electrical contacts to the third section of the first gate conductor. 
     
     
         12 . The method according to  claim 7 , a size of the undercut regions, and a difference in thickness of the gate insulator in the undercut regions relative to where the corner of the first gate conductor lacks the undercut regions in the isolation region, control overlap capacitance, breakdown voltage, and gate-induced drain leakage current. 
     
     
         13 . A method comprising:
 doping a substrate to have an active region bordered by an isolation region;   growing a gate insulator in the active region;   patterning a first gate conductor and a second gate conductor on and contacting the gate insulator, the first gate conductor and the second gate conductor are patterned to be perpendicular to one another, the first gate conductor is patterned to extend from the active region to the isolation region;   forming undercut regions in one side of the first gate conductor that is within the active region and in one side of the second gate conductor that is within the active region, where the undercut regions are formed at a corner of the first gate conductor and the second gate conductor where the first gate conductor and the second gate conductor contact the gate insulator; and   forming additional amounts of the gate insulator in the undercut regions, the gate insulator is relatively thicker in the undercut regions and is relatively thinner where the undercut regions are not present.   
     
     
         14 . The method according to  claim 13 , the first gate conductor and the second gate conductor are formed in the same process. 
     
     
         15 . The method according to  claim 13 , the second gate conductor is patterned to connect gate conductors of adjacent structures. 
     
     
         16 . The method according to  claim 13 , the undercut regions are formed on sides of the first gate conductor and the second gate conductor that face each other. 
     
     
         17 . The method according to  claim 13 , further comprising forming electrical contacts to the first gate conductor. 
     
     
         18 . The method according to  claim 13 , a size of the undercut regions, and a difference in thickness of the gate insulator in the undercut regions relative to where the the undercut regions are not present controls overlap capacitance, breakdown voltage, and gate-induced drain leakage current. 
     
     
         19 . The method according to  claim 13 , further comprising doping the active region to have a channel area. 
     
     
         20 . The method according to  claim 13 , the first gate conductor is patterned to have a first section, a second section, and a third section, the second section of the first gate conductor is between the first section and the third section of the first gate conductor, the first section of the first gate conductor is within the active region and has a first width, the third section of the first gate conductor is within the isolation region and has a second width that is greater than the first width, and the second section of the first gate conductor is within the active region and has a tapered width that tapers from the first width to the second width.