Inventor

INTRATER GIDEON

US38 patents

⚠️ This page may combine multiple inventors who share the name “INTRATER GIDEON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTRATER GIDEON

NAT SEMICONDUCTOR CORP

Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions

Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect

Selectively locking memory locations within a microprocessor&#39;s on-chip cache

Multi-processor element provided with hardware for software debugging

Memory management circuit which provides simulated privilege levels

Distributed directory for information stored on audio quality memory devices

Integrated digital signal processor/general purpose CPU with shared internal memory

Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active

Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect

Debug mechanism for parallel-operating DSP module and CPU core

Integrated data processing system including CPU core and parallel, independently operating DSP module

Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme

Mechanism for handling non-maskable interrupt requests received from different sources

Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions

Testing hooks for testing an integrated data processing system

Integrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modes

Processor core which provides a linear extension of an addressable memory space

Processor core which provides a linear extension of an addressable memory space

Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand

Integrated digital signal processor/general purpose CPU with shared internal memory

ADESTO TECHNOLOGIES CORP

Concurrent read and reconfigured write operations in a memory device

Memory device ultra-deep power-down mode exit control

Read latency reduction in a memory device

Ultra-deep power down mode control in a memory device

Read latency reduction in a memory device

Cached memory structure and operation

Cached memory structure and operation

Memory latency reduction in XIP mode

Concurrent read and reconfigured write operations in a memory device

Memory device having multiple read buffers for read latency reduction

Standby current reduction in memory devices

Support for improved throughput in a memory device

ADESTO TECH CORP

Read latency reduction in a memory device

Concurrent read and write operations in a serial flash device

KISHORE KARAGADA RAMARAO

Apparatus and method for processing template based user defined instructions

DIALOG SEMICONDUCTOR US INC

Latency reduction in SPI flash memory devices

BRAUN GUNNAR

User interface for facilitation of high level generation of processor extensions

GLOBALFOUNDRIES US INC

Low power standby mode for memory devices

Selectively locking memory locations within a microprocessor's on-chip cache