Inventor

NAIR RAVI

US96 patents

⚠️ This page may combine multiple inventors who share the name “NAIR RAVI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAIR RAVI

IBM

Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism

Method and apparatus for computer system reliability

Method and system for transparent dynamic optimization in a multiprocessing environment

Multiprocessor with pair-wise high reliability mode, and method therefore

Method and apparatus for fault-tolerance via dual thread crosschecking

Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system

Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions

Method and system for multiprocessor emulation on a multiprocessor host system

Silent store detection and recording in memory storage

Local bypass in memory computing

Low latency data exchange

Address generation in an active memory device

DRAM Cache with on-demand reload

Method and apparatus for monitoring event occurrences

Token based DMA

Approximate synchronization for parallel deep learning

Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host

Managing load and store operations using a storage management unit with data flow architecture

Processor bus for performance monitoring with digests

Distributed directory of named data elements in coordination namespace

Active memory device gather, scatter, and filter

On-chip traffic prioritization in memory

Power management for in-memory computer systems

Non-homogeneous multi-processor system with shared memory

Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors

Training machine learning systems

Dynamic update of the number of architected registers assigned to software threads using spill counts

Dynamic update of the number of architected registers assigned to software threads using spill counts

Locating node of named data elements in coordination namespace

On-chip traffic prioritization in memory

Implementing selective cache injection

Processor bus for performance monitoring with digests

Processor bus for performance monitoring with digests

Reduction of interrupts in remote procedure calls

Multichannel memory to augment local memory

Memory and logic chip stack with a translator chip

Streamlining data processing optimizations for machine learning workloads

Hybrid model for short text classification with imbalanced data

Relocation and persistence of named data elements in coordination namespace

Method, system, and computer program product for path-correlated indirect address predictions

Computer processing system employing an instruction schedule cache

Access of named data elements in coordination namespace

Coordination namespace processing

NAIR RAVI

Virtualizing the execution of homogeneous parallel systems on heterogeneous multiprocessor platforms

Hybrid mechanism for more efficient emulation and method therefor

Method and system for efficient emulation of multiprocessor memory consistency

Hybrid mechanism for more efficient emulation and method therefor

FLEISCHER BRUCE M

Predication in a vector processor

Predication in a vector processor

Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry